<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: PIT clock source setting RT1176 in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/PIT-clock-source-setting-RT1176/m-p/1427352#M18743</link>
    <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;PIT1 is clocked from BUS_CLK_ROOT and so if you reduce this you will reduce it for all other modules using the same clock root.&lt;/P&gt;&lt;P&gt;PIT1 channels 0 and 1 can however be chained to build a 64 bit counter, which allows increasing the maximum period by 4Gx. &lt;EM&gt;Even at 240MHz this gives about 2'500 years before it overflows.&lt;/EM&gt;&lt;BR /&gt;&lt;BR /&gt;PIT 2 is clocked from BUS_LPSR_CLK_ROOT and so, if your design can use a much slower BUS_LPSR_CLK_ROOT, (much) longer 32 bit periods can be achieved. Also PIT 2's channels 0 and 1 can be chained to further increase the maximum period.&lt;BR /&gt;Eg. if BUS_LPSR_CLK can be set to (OSC_24M / 256) the PIT 2 can count up to 12.7 hours before overflowing.&lt;BR /&gt;The same using two chained channels can count to 6 million years before overflowing.&lt;BR /&gt;&lt;BR /&gt;Whatever solution is used a PIT period interrupt can also be used as a counter so that software can further extend the period of software timers beyond that possible with the HW limitation.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Sun, 13 Mar 2022 20:37:59 GMT</pubDate>
    <dc:creator>mjbcswitzerland</dc:creator>
    <dc:date>2022-03-13T20:37:59Z</dc:date>
    <item>
      <title>PIT clock source setting RT1176</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/PIT-clock-source-setting-RT1176/m-p/1427316#M18741</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;&lt;P&gt;the PIT seems to be a very simple peripheral to use. But I couldn't find the clock source setting for PIT in the MCUXpresso configuration tools like other peripherals like ADC, CAN etc. Why?&lt;/P&gt;&lt;P&gt;What happen if I want to build a very very very long timer, like days? the default value 240MHz ist too fast.&lt;/P&gt;&lt;P&gt;Okay, maybe I can change the bus clock root setting, but there are many other devices like ADC_ETC also hanging on the (240MHz) bus clock root , which I dont want to change them.&amp;nbsp;&lt;/P&gt;&lt;P&gt;What should I do?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="auftrag2021_0-1647124551389.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/173423iE4597B8E227E324E/image-size/large?v=v2&amp;amp;px=999" role="button" title="auftrag2021_0-1647124551389.png" alt="auftrag2021_0-1647124551389.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 12 Mar 2022 22:42:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/PIT-clock-source-setting-RT1176/m-p/1427316#M18741</guid>
      <dc:creator>auftrag2021</dc:creator>
      <dc:date>2022-03-12T22:42:02Z</dc:date>
    </item>
    <item>
      <title>Re: PIT clock source setting RT1176</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/PIT-clock-source-setting-RT1176/m-p/1427352#M18743</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;PIT1 is clocked from BUS_CLK_ROOT and so if you reduce this you will reduce it for all other modules using the same clock root.&lt;/P&gt;&lt;P&gt;PIT1 channels 0 and 1 can however be chained to build a 64 bit counter, which allows increasing the maximum period by 4Gx. &lt;EM&gt;Even at 240MHz this gives about 2'500 years before it overflows.&lt;/EM&gt;&lt;BR /&gt;&lt;BR /&gt;PIT 2 is clocked from BUS_LPSR_CLK_ROOT and so, if your design can use a much slower BUS_LPSR_CLK_ROOT, (much) longer 32 bit periods can be achieved. Also PIT 2's channels 0 and 1 can be chained to further increase the maximum period.&lt;BR /&gt;Eg. if BUS_LPSR_CLK can be set to (OSC_24M / 256) the PIT 2 can count up to 12.7 hours before overflowing.&lt;BR /&gt;The same using two chained channels can count to 6 million years before overflowing.&lt;BR /&gt;&lt;BR /&gt;Whatever solution is used a PIT period interrupt can also be used as a counter so that software can further extend the period of software timers beyond that possible with the HW limitation.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 13 Mar 2022 20:37:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/PIT-clock-source-setting-RT1176/m-p/1427352#M18743</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2022-03-13T20:37:59Z</dc:date>
    </item>
  </channel>
</rss>

