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    <title>topic Re: Multi-core debugging on RT11776 causing peripheral initialisation problems in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Multi-core-debugging-on-RT11776-causing-peripheral/m-p/1416567#M18433</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/185524"&gt;@D_TTSA&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;I can't image why the M4 core initializing breakpoint can cause LPSPI accessing spi-flash fail. Maybe it's a timing issue? Does the external spi-flash need reset when reboot the system?&lt;/P&gt;
&lt;P&gt;Can you use a oscilloscope or a logic analyzer to trace the SPI signal?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Jing&lt;/P&gt;</description>
    <pubDate>Mon, 21 Feb 2022 07:59:18 GMT</pubDate>
    <dc:creator>jingpan</dc:creator>
    <dc:date>2022-02-21T07:59:18Z</dc:date>
    <item>
      <title>Multi-core debugging on RT11776 causing peripheral initialisation problems</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Multi-core-debugging-on-RT11776-causing-peripheral/m-p/1412221#M18289</link>
      <description>&lt;P&gt;Good day&lt;/P&gt;&lt;P&gt;I am developing a multi-core project on the RT1176 with the M7 core as the master and the M4 as the slave. By default, when I debug the processor, the launch configurations halt each core at automatically created breakpoints at the top of the M7's and M4's main()s.&lt;/P&gt;&lt;P&gt;In my project, the M7 boots the M4 just before the M7 starts initialising an external flash module I am using. I am using&amp;nbsp;LPSPI to communicate with this module.&lt;/P&gt;&lt;P&gt;After some testing, I saw that the flash initialisation was failing when I debugged the processor. I know the init was failing because I could not read or write the flash module when debugging. This did not occur if the processor was run from a POR (Power On Reset), or from a full system reset.&lt;/P&gt;&lt;P&gt;After a lot of pain and more testing, I found that disabling the debugger's automatic breakpoint at the top of the M4's main() fixed this problem.&lt;/P&gt;&lt;P&gt;To discover why this was the case, I enabled the breakpoint in the M4's main() and then debugged the processor again. I ran the M7 debug but did not run the M4 - it remained halted on the automatic breakpoint. After a while, I paused the M7 core to see where it was. It was hanging in LPSPI_MasterTransferBlocking() - no matter how long I left it to run. I ran and paused it, but it was always somewhere in this function. None of the code in the M7's main() below my flash init function was executed unless I ran the M4's debug.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="D_Tram23_0-1644510843518.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/170198iE157B8F338CC0DE7/image-size/large?v=v2&amp;amp;px=999" role="button" title="D_Tram23_0-1644510843518.png" alt="D_Tram23_0-1644510843518.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;My colleague ran the same code, but the M7 hung in a different function call. However, he had the same problem with the flash communication not working after a debug.&lt;/P&gt;&lt;P&gt;Anyway, the better solution was to move the code that boots the M4 to &lt;STRONG&gt;after&lt;/STRONG&gt; all the M7's peripheral init code has been executed. This way, even though the M4's main() breakpoint still halts the M7, this does not break any of the M7's functionality.&lt;/P&gt;&lt;P&gt;I hope that my above explanation can be of some use to someone in future so that they don't have to suffer through the same painful process.&lt;/P&gt;&lt;P&gt;I would like NXP's technical support team to explain&amp;nbsp;&lt;STRONG&gt;why&lt;/STRONG&gt; the automatically created breakpoint at the top of the M4's main() makes the M7 hang.&lt;/P&gt;</description>
      <pubDate>Fri, 11 Feb 2022 06:04:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Multi-core-debugging-on-RT11776-causing-peripheral/m-p/1412221#M18289</guid>
      <dc:creator>D_TTSA</dc:creator>
      <dc:date>2022-02-11T06:04:30Z</dc:date>
    </item>
    <item>
      <title>Re: Multi-core debugging on RT11776 causing peripheral initialisation problems</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Multi-core-debugging-on-RT11776-causing-peripheral/m-p/1416567#M18433</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/185524"&gt;@D_TTSA&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;I can't image why the M4 core initializing breakpoint can cause LPSPI accessing spi-flash fail. Maybe it's a timing issue? Does the external spi-flash need reset when reboot the system?&lt;/P&gt;
&lt;P&gt;Can you use a oscilloscope or a logic analyzer to trace the SPI signal?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Jing&lt;/P&gt;</description>
      <pubDate>Mon, 21 Feb 2022 07:59:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Multi-core-debugging-on-RT11776-causing-peripheral/m-p/1416567#M18433</guid>
      <dc:creator>jingpan</dc:creator>
      <dc:date>2022-02-21T07:59:18Z</dc:date>
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