topic Re: RT1173 JTAG/SWD connection problems in i.MX RT Crossover MCUs

RT1173 JTAG/SWD connection problems

Stephan_ — Fri, 04 Feb 2022 14:02:24 GMT

Hi there,

I'm working with an iMX RT1173 on an custom board. We've checked supply voltages and clock signals, all seems to be fine. Also we've compared our schematic against MIMXRT1170-EVK and can't see any major differences in supply, clock or JTAG/SWD. But still I'm not able to connect to CPU with Debugger.

Using Lauterbach yTrace I got message 'Running (Core Power Down)' and DAP: CorePowerDown CTRLSTAT = 0xd0000000 just after command 'SYStem.PowerUp'.

Using Segger JLink I got 3 times "Found SW-DP with ID 0x6BA02477 / Failed to power up DAP" and then "Connection failed.".

I've checked reset lines, reset signal seems to be good. JTAG/SWD itself seems to be working, otherwise the CTRLSTAT bit for 'system power up request' will not be working (I assume). CTRLSTAT register shows missing ack for 'Debug Power Up'.

Can someone give me a hint where the problem can be located?

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Tue, 08 Feb 2022 07:52:06 GMT

Hi @Stephan_ ,

Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.

Please help check these points:

1. Find a Segger JLINK, then use the JLINK command to connect your board, with SWD interface, whether you can find the ARM core or not?

If you can't find the ARM core, hardware have issues.

2. Then please refer to this document:

https://www.nxp.com/webapp/Download?colCode=MIMXRT1170HDUG&location=null

And datasheet power sequence

Do you match the power sequence?

3. check the boot_cfg, boot_mod pin configuration.

You must let the board find the ARM core at first, otherwise, you need to check your hardware, design, hardware solder, power sequence, etc. as it is totally not work.

You even can check the related point with the MIMXRT1170-EVK board.

Wish it helps you!

Best Regards,

Kerry

Re: RT1173 JTAG/SWD connection problems

Stephan_ — Tue, 08 Feb 2022 10:17:23 GMT

Hi,

power sequence look's good except an additional 150ms delay before POR_B due to external reset component in power supply.

We've done some research and it looks like a problem with our flash. We've attach a QSPI Nor Flash at FlexSPI2 (using secondary pin group). After I changed the boot config to serial loader I can access using debugger.

But now I ran into next issues. After serial loader was active I changed fuse bits with MCU Boot Utility, I changed fuses 0x9A0 to 0x00000006 (set FLASH_CONNECTION_SEL to 'PORTB CS0' and FLEXSPI_SPI_GROUP_SEL to 'secondary'). After reboot of device I still can access via JTAG but there is no connection with MCU Boot Utility anymore.

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Fri, 11 Feb 2022 04:43:23 GMT

Hi @Stephan_

So, your used flexSPI pin is not the same as the MIMXRT1170-EVK board, right?

As I know, the debugger download code to the flash also related to the program flashdirver, and this flashdriver will defines the related interface, different debugger the flashdriver file is not the same, I don't have your Lauterbach, so I don't know your related flashdriver code is using which interface.

Now, you can debug the code, I think you can try to download the simple code to the internal RAM, whehter that works, if that works OK, just the flash can't work, then I think still need to check your flash area.

Now, you connect to the flexSPI2 using the following interface?

In fact, when you don't familiar with the chip, we don't recommend you burn the fuse.

You also can try to modify this code and run it in the internal ram, whether your external flash works ok or not?

SDK_2_11_0_MIMXRT1170-EVK\boards\evkmimxrt1170\driver_examples\flexspi\nor\polling_transfer\cm7

You need to change the pinmux the related pin, and the interface, test this code at first.

Best Regards,

Kerry

Re: RT1173 JTAG/SWD connection problems

Stephan_ — Fri, 11 Feb 2022 13:24:04 GMT

Hi,

according Lauterbach support it should be possible to access QSPI flash at FlexSPI2.

Wr're using 2nd pin group, so correct tabel from TRM should be:

Actual I use a new hardware. Boot mode is set to 'Internal' and no fuses are burned.MCU start to 'Serial Download', I can connect using 'MCU Boot Utility'.

I've managed to change polling transfer example. Debug output shows "FLEXSPI example started!" and "Vendor ID: 0x1" (I think the AT25FF161A has vendor ID 0x1F). Call to function flexspi_nor_enable_quad_mode() won't return. I think there's still no connection to flash.

When I got it right there is no need to change fuse for 2nd pin group to this test, let me know if I had to.

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Mon, 14 Feb 2022 03:02:16 GMT

Hi @Stephan_

Thanks for your effort and the new board without the fuse modification.

1. Which QSPI flash chip you are using now in your own new board? The same as MIMXRT1170-EVK, and just the flexSPI interface is not the same? IS25WP128-JBLE?

As different QSPI, the LUT command may have difference.

2. About the Lauterbach, I am not use your flashdriver firmware can support it, it may normally support the flexSPI1 in the firmware. If you have the Lauterbach flashdriver source code, you can check it.

3. About the MCUbootUtility with new board and can't connect, it should be related to the configuration, as you are using the flexSPI2.

Please share me your flexspi QSPI connection schematic, I need to check it.

4. About polling transfer example, which detail point you have modified, please list all the item which you have modified, I need to check it.

Best Regards,

Kerry

Re: RT1173 JTAG/SWD connection problems

Stephan_ — Mon, 14 Feb 2022 07:38:07 GMT

Hello,

I try to answer your questions as good as possible

1 - We're using Adesto AT25FF161A which is quite simmilar to the AS25SF series.

2 - According Lauterbach Support the flash connection should working, but I'm on to clarify this in parallel.

3 - Here are the schematic part with flash connection. The CS wire is changed to CS0 on my board, actual PCB accidentally connected flash to CS1.

4 - I've added new pins in 'pin configuration' from MCUXpresso. Added used peripherals and updated code with MCUXpresso. Changed definitions EXAMPLE_FLEXSPI, XAMPLE_FLEXSPI_AMBA_BASE, EXAMPLE_FLEXSPI_CLOCK, FLASH_PORT to FlexSPI2. Changed configuration to run from RAM. Generated AXF file is loaded with Lauterbach Debugger. I've added modified project so you can diff it.

I hope this information helps to analyze the problem. If you need further information just let me know.

Best Regards

Stephan

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Tue, 15 Feb 2022 03:18:11 GMT

Hi @Stephan_

Seems you didn't modify the LUT, please modify the LUT like this:

const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
/* Normal read mode -SDR */
[4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
[4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Fast read mode - SDR */
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),

/* Fast read quad mode - SDR */
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18),
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),

/* Read extend parameters */
[4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x81, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),

/* Write Enable */
[4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Erase Sector */
[4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xD8, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),

/* Page Program - single mode */
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Page Program - quad mode */
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Read ID */
[4 * NOR_CMD_LUT_SEQ_IDX_READID] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),

/* Enable Quad mode */
[4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =//kerry 0X01 ->0X31
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x31, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),

/* Enter QPI mode */
[4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Exit QPI mode */
[4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xF5, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),

/* Read status register */
[4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),

/* Erase whole chip */
[4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
};

Your QE bit also need to be modified:

App.h,

#define FLASH_QUAD_ENABLE 0X02//kerry 0x40U->0x02

As the QE bit is the status register 2, bit 1:

https://www.dialog-semiconductor.com/sites/default/files/2022-01/DS-AT25FF161A-182J-112021.pdf

Wish it helps you!

Best Regards,

Kerry

Re: RT1173 JTAG/SWD connection problems

Stephan_ — Tue, 15 Feb 2022 07:51:29 GMT

Hello,

I've tried with your modifications but still same behavior, output "Vendor ID: 0x1" which is not correct and program stuck in function call "flexspi_nor_enable_quad_mode(EXAMPLE_FLEXSPI);".

I've PCB with attach logic analyzer on QSPI lanes but I can't see any operation on the lines. It seems like the programm dosen't access the SPI flash in any way.

Can you have a look at "flexspi_clock_init()", I'm not sure with the call to "CLOCK_SetRootClockMux()".

Best Regards

Stephan

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Tue, 15 Feb 2022 09:52:02 GMT

Hi @Stephan_ ,

Thanks for your information.

If your flexSPI2 even don't have the wave, it means, the code still not work, still need to check the flexSPI detail modification, maybe something is lost.

About CLOCK_SetRootClockMux(), please check the details, whether it configure the flexSPI2 clock, at least the flexspi2 should have clock out.

Best Regards,

Kerry

Re: RT1173 JTAG/SWD connection problems

Stephan_ — Mon, 21 Feb 2022 14:58:00 GMT

Hi,

I've checked the clock MUX values, but according given documentation the value should be right:

Meanwhile Lauterbach Support was able to get flash working with uTrace Debugger. I've done some short tests and it seems to be working, so it looks like the problem is not located on PCB. I think there is still some modification missing in example project, but have no glue where...

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Tue, 22 Feb 2022 03:39:55 GMT

Hi @Stephan_

Thanks for your updated information.

1. About the flexspi2 clock configuration, you are correct:

static inline void flexspi_clock_init(void)
{
/*Clock setting for flexspi1*/
CLOCK_SetRootClockDiv(kCLOCK_Root_Flexspi1, 2);
CLOCK_SetRootClockMux(kCLOCK_Root_Flexspi1, 0);
/*Clock setting for flexspi2*/
CLOCK_SetRootClockDiv(kCLOCK_Root_Flexspi2, 2);
CLOCK_SetRootClockMux(kCLOCK_Root_Flexspi2, 0);
}

/* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);

The API will help to configure the flexSPI2.

When you test the polling code, you run it in RAM?

2. Lauterbach Support was able to get flash working with uTrace Debugger

Please give me some debug screenshot, whether the flash address is correct? I mean, whether your code is downloaded to the external flash or not?

If it can download code to the flash, whether boot works or not after you modify the fuse:

1). FLEXSPI_INSTANCE fuse/boot pin is 1.
2). FLEXSPI_PIN_GROUP_SEL fuse bit is 0.

Best Regards,

Kerry

Re: RT1173 JTAG/SWD connection problems

Stephan_ — Tue, 22 Feb 2022 08:08:24 GMT

Hello,

my test programm is running in RAM, I've use the setting you described in screenshot.

According the flashed code, when try to run from flash I use 'release' configuration in MCUXpresso. With Lauterbach I load axf file which write program code to flash. When I dump the first addresses from flash it look like this:

I've set fuses as follows:

We're using 2nd pin group, so there is FLEXSPI_PIN_GROUP_SEL set to 1.

I've opened another thread about generation bootable binary file (Create bootable image for RT1173 QSPI flash - NXP Community), so I think we can stick to 'run from RAM' configuration and try to get polling example working.

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Wed, 23 Feb 2022 02:11:16 GMT

Hi @Stephan_

1. Seems your Lauterbach already enter the debug mode, please run it directly.

Then check the printf information, whether the external QSPI flash runs OK or not?

You can see the printf information through the UART interface.

GPIO_AD_25->LPUART1_RXD

GPIO_AD_24->LPUART1_TXD

2. MCUBootUtlity, seems you also connect to the chip, please select bootDevice Memory

In the Boot Device Memory, you can readout the memory.

In the connection area, you can select One Step to connect your board.

Best Regards,

Kerry

Re: RT1173 JTAG/SWD connection problems

Stephan_ — Wed, 23 Feb 2022 07:43:57 GMT

Hello,

as already stated in comment above I'm able to run the modified polling example and get some output on debug port but with wrong manufaturer ID and program stuck at "flexspi_nor_enable_quad_mode(EXAMPLE_FLEXSPI);".

MCU Boot Utility can connect to MCU but is not capable to access QSPI Flash at FlexSPI2 (2nd pin group). I'm already in contact with NXP FAE but there is still no solution.

Best Regards
Stephan

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Wed, 23 Feb 2022 09:58:42 GMT

Hi @Stephan_ ,

Thanks for your information, as I don't have the RT1170 board which connect the QSPI in the flexSPI2, so I can't test it direct.

Now, seems only your debugger Lauterbach can download the code, but I find your downloaded code is not correct, it didn't contains the FCB, IVT, so the image is totally wrong, could you please use my attached led_blinky and test it with your Lauterbach?

My image is correct:

From 0X600004000 FCB:

0X60001000 IVT:

From 0X60002000, app:

Please use your debugger test my .axf, whether the led code function works or not? Test it in the internal boot mode directly.

Any updated information, kindly let me know.

Best Regards,

Kerry

Re: RT1173 JTAG/SWD connection problems

Stephan_ — Wed, 23 Feb 2022 11:00:22 GMT

Hi,

i've tried your blinky AXF. Unfortunately I've no access to pin M13 on my board, I've an LED on R10, but not yet managed to get an blinky work with this pin.

Nethertheless, when I program your AXF and reboot in 'internal Boot' configuration I can't access with Debugger (Core Power Down), so it seems MCU Bootloader can't load image. Also MCU Boot Utility have no access.

I've managed to get an binary image from MCU expresso with IVT and FCB. Not sure why, but after changing BOARD_FLASH from 0x3000000 to 0x6000000 in the Release linke file the following lines are missing:

/* Image Vector Table and Boot Data for booting from external flash */
.boot_hdr : ALIGN(4)
{
FILL(0xff)
. = 0x400 ;
__boot_hdr_start__ = ABSOLUTE(.) ;
KEEP(*(.boot_hdr.conf))
. = 0x1000 ;
__boot_hdr_ivt_loadaddr__ = ABSOLUTE(.) ;
KEEP(*(.boot_hdr.ivt))
. = 0x1020 ;
__boot_hdr_boot_data_loadaddr__ = ABSOLUTE(.) ;
KEEP(*(.boot_hdr.boot_data))
. = 0x1030 ;
__boot_hdr_dcd_loadaddr__ = ABSOLUTE(.) ;
KEEP(*(.boot_hdr.dcd_data))
__boot_hdr_end__ = ABSOLUTE(.) ;
. = 0x2000 ;
} >BOARD_FLASH

After adding manual and switch off managed linker files in project configuration I got a binary with FCB and IVT. The binary is attached, so you can have a quick look if you find an error. I got same behavior with your and mine binary file. In 'internal Boot' the MCU won't start. In 'Boot from Fuses' the MCU will go into Serial Download.

Re: RT1173 JTAG/SWD connection problems

Stephan_ — Wed, 23 Feb 2022 14:56:23 GMT

Hi,

I've managed to build an working blinky example for my board, I've to use another LED on Pin R13, Pin R10 can't be used on our chip due to tamper unit.

When I run the application from RAM it works finde. When I load the binary image to flash to MCU won't load the programm. I've attach the binary file so you can check if FCB and IVT correct. Is there any intergrated checksum or other parts which potentially use wrong address since changed BOAR_FLASH address?

Is there any way to check why internal MCU Bootloader won't load image?

I'm going to try my image on PCB with connected logic analyzer to check which sectors read from flash during startup.

Best Regards

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Thu, 24 Feb 2022 02:35:15 GMT

Hi @Stephan_ ,

You are right, that's why my previous reply share you the code project, which I also add the FCB, IVT in the ld file.

Now, I checked your generated .bin, it is the correct app which contains FCB, IVT, app.

I mean, use your debugger Lauterbach , as previous reply, you can use it download code to the 0X60000000, so whether you can use Lauterbach download the new complete app.bin which contains FCB and IVT?

Best Regards,

Kerry

Re: RT1173 JTAG/SWD connection problems

kerryzhou — Thu, 24 Feb 2022 02:39:53 GMT

Hi @Stephan_ ,

Please also help to check the hardware, BOOT_CFG configure, do you select it as the QSPI, this is also important:

Until now, your app image is correct, please also use your previously working Lauterbach download the .axf or the .bin, whehter that still can download the code, what's the result.

Any updated information, please kindly let me know.

Best Regards,

Kerry