https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Understanding-EVK-Operation/m-p/1407767#M18184 <P>Ok, I guess I may have figured this out myself.&nbsp; From the reference manual section 27.5.15, FlexSPI always supports XIP regardless of flash device if placed in Advanced High Performance Bus (AHB) access mode.&nbsp; In addition, u-boot subsequently copies itself into external RAM (0x80000000) area for better execution performance.</P> Tue, 01 Feb 2022 22:01:55 GMT jautry 2022-02-01T22:01:55Z https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Understanding-EVK-Operation/m-p/1406869#M18166 <P>I am trying to understand the ROM boot process.&nbsp; I see the IVT table has start addresses in the flash 0x60000000 range.&nbsp; I look at the boot data start and it also has address in flash 0x60000000 range.&nbsp; I then look at the u-boot map file and all addresses are in the flash 0x60000000 range.&nbsp; The XIP fuse setting is at 0.&nbsp; I thought the flash code was supposed to be copied into OCRAM and executed from there but I see no addressing in the OCRAM area.&nbsp; How is this operating?&nbsp; What am I not understanding?</P> Sun, 30 Jan 2022 03:36:39 GMT https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Understanding-EVK-Operation/m-p/1406869#M18166 jautry 2022-01-30T03:36:39Z https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Understanding-EVK-Operation/m-p/1407767#M18184 <P>Ok, I guess I may have figured this out myself.&nbsp; From the reference manual section 27.5.15, FlexSPI always supports XIP regardless of flash device if placed in Advanced High Performance Bus (AHB) access mode.&nbsp; In addition, u-boot subsequently copies itself into external RAM (0x80000000) area for better execution performance.</P> Tue, 01 Feb 2022 22:01:55 GMT https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Understanding-EVK-Operation/m-p/1407767#M18184 jautry 2022-02-01T22:01:55Z