<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: System PLL PFD hardfault error while booting to SDRAM in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394548#M17861</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/60336"&gt;@kerryzhou&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;Thanks for your support.&lt;/P&gt;&lt;P&gt;I referenced wiced_iperf_4343W exmaples from SDK2.7.0 and commented "BOARD_USDHCClockConfiguration()" and "CLOCK_InitSysPfd(kCLOCK_Pfd2, 0x12U);" in main.c.&lt;/P&gt;&lt;P&gt;Please referenced the attched file which I added symbol and memory configs for more details.&lt;/P&gt;&lt;P&gt;If you need more informations, please tell me. Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best Regards.&lt;/P&gt;&lt;P&gt;Kyle&lt;/P&gt;</description>
    <pubDate>Wed, 05 Jan 2022 04:49:11 GMT</pubDate>
    <dc:creator>KyleHsieh</dc:creator>
    <dc:date>2022-01-05T04:49:11Z</dc:date>
    <item>
      <title>System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394153#M17845</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I defined the following symbols to booting to SDRAM in iperf project,&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="symbol.JPG" style="width: 788px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166641i2248812A7F2988E9/image-size/large?v=v2&amp;amp;px=999" role="button" title="symbol.JPG" alt="symbol.JPG" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="memory details.JPG" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166642i426C563AD2CB14E0/image-size/large?v=v2&amp;amp;px=999" role="button" title="memory details.JPG" alt="memory details.JPG" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="heap and stack.JPG" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166643i153E7743311976ED/image-size/large?v=v2&amp;amp;px=999" role="button" title="heap and stack.JPG" alt="heap and stack.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;After the above configs, my project could have more&lt;SPAN&gt;&amp;nbsp;code space to porting other functions.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="console.JPG" style="width: 834px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166644i8A37FFC8665174C3/image-size/large?v=v2&amp;amp;px=999" role="button" title="console.JPG" alt="console.JPG" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But we encounter the hardfault error while debugging the project.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="hardfault.JPG" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166646i6B248B45AD68DB32/image-size/large?v=v2&amp;amp;px=999" role="button" title="hardfault.JPG" alt="hardfault.JPG" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;This error only can be passed&amp;nbsp;when this config was commented out in CLOCK_InitSysPfd(kCLOCK_Pfd2, 0x12U); //configure system pll PFD2 fractional divider to 18&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;May I ask why this issue only happend on SDRAM instead internal RAM?&lt;/P&gt;&lt;P&gt;Looking forward your reply.&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best Regards.&lt;/P&gt;&lt;P&gt;Kyle&lt;/P&gt;</description>
      <pubDate>Tue, 04 Jan 2022 09:39:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394153#M17845</guid>
      <dc:creator>KyleHsieh</dc:creator>
      <dc:date>2022-01-04T09:39:17Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394520#M17859</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/195330"&gt;@KyleHsieh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Please tell me which detail SDK code you are refering? as we have two iperf project:lwip_iperf and wifi_iperf.&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Please also tell me which detail&amp;nbsp;&lt;SPAN&gt;symbols&amp;nbsp;you have added?&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp;As you already modified the project name, so I don't know your related SDK code, I just can get the information that you are using RT1060.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; Your hardfault should related to the SDRAM and the cache match issues.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; You also mentioned, when comment&amp;nbsp;CLOCK_InitSysPfd(kCLOCK_Pfd2, 0x12U);&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; Please also tell me which detail files?&amp;nbsp; This is related to the SEMC clock, which is the SDRAM clock.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Waiting for your detail information.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Kerry&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 05 Jan 2022 03:26:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394520#M17859</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-01-05T03:26:01Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394548#M17861</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/60336"&gt;@kerryzhou&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;Thanks for your support.&lt;/P&gt;&lt;P&gt;I referenced wiced_iperf_4343W exmaples from SDK2.7.0 and commented "BOARD_USDHCClockConfiguration()" and "CLOCK_InitSysPfd(kCLOCK_Pfd2, 0x12U);" in main.c.&lt;/P&gt;&lt;P&gt;Please referenced the attched file which I added symbol and memory configs for more details.&lt;/P&gt;&lt;P&gt;If you need more informations, please tell me. Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best Regards.&lt;/P&gt;&lt;P&gt;Kyle&lt;/P&gt;</description>
      <pubDate>Wed, 05 Jan 2022 04:49:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394548#M17861</guid>
      <dc:creator>KyleHsieh</dc:creator>
      <dc:date>2022-01-05T04:49:11Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394553#M17862</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/195330"&gt;@KyleHsieh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Your SDK is very old, please check the newest SDK2.10.1:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://mcuxpresso.nxp.com/en/builder?hw=EVK-MIMXRT1060" target="_blank"&gt;https://mcuxpresso.nxp.com/en/builder?hw=EVK-MIMXRT1060&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Whether you still have the issues or not?&lt;/P&gt;
&lt;P&gt;&amp;nbsp; If you use the newest SDK also have the issues, then you can upload your modified project based on the SDK2.10.1, then I will help to check it on my side.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Kerry&lt;/P&gt;</description>
      <pubDate>Wed, 05 Jan 2022 05:10:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394553#M17862</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-01-05T05:10:10Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394592#M17863</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/60336"&gt;@kerryzhou&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;Thanks. I will try the &lt;SPAN&gt;SDK2.10.1 for test.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;May I ask is there any project which can replaced "wiced_iperf_4343W" example&amp;nbsp;on SDK2.10.1 ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We would like to build a project which can cypress WiFi connected over USDHC/SDIO&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best Regards.&lt;/P&gt;&lt;P&gt;Kyle&lt;/P&gt;</description>
      <pubDate>Wed, 05 Jan 2022 06:12:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394592#M17863</guid>
      <dc:creator>KyleHsieh</dc:creator>
      <dc:date>2022-01-05T06:12:49Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394609#M17864</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/195330"&gt;@KyleHsieh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Please test SDK2.9.3, this is the last version that contains your mentioned cypress wifi:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://mcuxpresso.nxp.com/en/builder?hw=EVK-MIMXRT1060&amp;amp;rel=465" target="_blank"&gt;https://mcuxpresso.nxp.com/en/builder?hw=EVK-MIMXRT1060&amp;amp;rel=465&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Please download it, and test this version, whether you can reproduce the issues or not.&lt;/P&gt;
&lt;P&gt;&amp;nbsp; From SDK2.10.0, the cypress wifi is removed, the SDK only add the NXP own wifi chip.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Wish it helps you!&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Kerry&lt;/P&gt;</description>
      <pubDate>Wed, 05 Jan 2022 06:40:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1394609#M17864</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-01-05T06:40:52Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1395290#M17887</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/60336"&gt;@kerryzhou&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;Thank you for your support.&lt;/P&gt;&lt;P&gt;I used SDK2.9.1 for test and found "BOARD_USDHCClockConfiguration();" has been removed from main function in SDK2.9.1.&lt;/P&gt;&lt;P&gt;But if I add&amp;nbsp;BOARD_USDHCClockConfiguration() back to set USDHC clock and boot to SDRAM.&lt;/P&gt;&lt;P&gt;This issue still reduplicated.&lt;/P&gt;&lt;P&gt;May I ask how could we config SEMC clock if we would like to boot in SDRAM?&lt;/P&gt;&lt;P&gt;And why did "BOARD_USDHCClockConfiguration();" removed from SDK2.9.1?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best Regards.&lt;/P&gt;&lt;P&gt;Kyle&lt;/P&gt;</description>
      <pubDate>Thu, 06 Jan 2022 04:17:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1395290#M17887</guid>
      <dc:creator>KyleHsieh</dc:creator>
      <dc:date>2022-01-06T04:17:56Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1395439#M17893</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/195330"&gt;@KyleHsieh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;The code removed in the new SDK, it should be the SDK team find with that code meet some bugs, so remove it.&lt;/P&gt;
&lt;P&gt;&amp;nbsp; So, I think you don't need to add it, just based on the new SDK project, and work on it, whether you still have the hardfault issues?&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Kerry&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 06 Jan 2022 07:49:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1395439#M17893</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-01-06T07:49:06Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1395503#M17895</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/60336"&gt;@kerryzhou&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;The CCM clock tree is as below,&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="clock tree.png" style="width: 921px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166859i807CD70E2BE7B55A/image-size/large?v=v2&amp;amp;px=999" role="button" title="clock tree.png" alt="clock tree.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Both USDHC device and SEMC device are connected to PLL2-PFD2.&lt;/P&gt;&lt;P&gt;After the main function boot in SDRAM, the "&lt;SPAN&gt;CLOCK_InitSysPfd(kCLOCK_Pfd2, 0x12U);" set the&amp;nbsp;PLL2-PFD2 clock.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Is this action affect boot in SDRAM?&lt;/P&gt;&lt;P&gt;How could we set the semc clock as PLL3-PFD1 in SDK?&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;Best Regards.&lt;/P&gt;&lt;P&gt;Kyle&lt;/P&gt;</description>
      <pubDate>Thu, 06 Jan 2022 08:59:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1395503#M17895</guid>
      <dc:creator>KyleHsieh</dc:creator>
      <dc:date>2022-01-06T08:59:09Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1395526#M17896</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/195330"&gt;@KyleHsieh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;Thanks for your updated information.&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;If your SEMC already connected to the&amp;nbsp;&lt;SPAN&gt;PLL2-PFD2, then you change the clock, the SDRAM must be influenced.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; About how to configure the SEMC to use the&amp;nbsp;PLL3-PFD1, do you use the MCUXPresso IDE project, it has the clock CFG, you can use the CFG tool to configure it.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; ConfigTools-&amp;gt;clock&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Wish it helps you!&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Kerry&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 06 Jan 2022 09:41:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1395526#M17896</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-01-06T09:41:06Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1397959#M17955</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/60336"&gt;@kerryzhou&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;For now, we could boot to SDRAM by config "Extra linker script input section" as "NCACHE_REGION" intead of "BOARD_SDRAM_NONCACHEABLE" on SDK2.9.3.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Extra linker script input section.JPG" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/167375i322DE5F05260FF20/image-size/large?v=v2&amp;amp;px=999" role="button" title="Extra linker script input section.JPG" alt="Extra linker script input section.JPG" /&gt;&lt;/span&gt;&lt;BR /&gt;What's the difference between using Region "NCACHE_REGION" and "BOARD_SDRAM_NONCACHEABLE"?&lt;/P&gt;&lt;P&gt;Why did this project(Attachment.zip) config as BOARD_SDRAM_NONCACHEABLE in this case(&lt;A href="https://community.nxp.com/t5/i-MX-RT/Load-instructions-into-RAM-from-external-flash-while-executing/m-p/951716" target="_blank"&gt;https://community.nxp.com/t5/i-MX-RT/Load-instructions-into-RAM-from-external-flash-while-executing/m-p/951716&lt;/A&gt;)?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Thank you.&lt;/P&gt;&lt;P&gt;Best Regards.&lt;/P&gt;&lt;P&gt;Kyle&lt;/P&gt;</description>
      <pubDate>Wed, 12 Jan 2022 08:56:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1397959#M17955</guid>
      <dc:creator>KyleHsieh</dc:creator>
      <dc:date>2022-01-12T08:56:34Z</dc:date>
    </item>
    <item>
      <title>Re: System PLL PFD hardfault error while booting to SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1398018#M17956</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/195330"&gt;@KyleHsieh&lt;/a&gt;&amp;nbsp;,&amp;nbsp;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Please check the MCUXPresso MCU settings, you can find the detail define for the region:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="kerryzhou_0-1641980537249.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/167396i157319BC913C690B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="kerryzhou_0-1641980537249.png" alt="kerryzhou_0-1641980537249.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Normally,&amp;nbsp;&lt;SPAN&gt;NCACHE_REGION is the memory section in the SDRAM.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;When you use the SDRAM, you need to enable the DCD:XIP_BOOT_HEADER_DCD_ENABLE=1 and&amp;nbsp;SKIP_SYSCLK_INIT symbols.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Wish it helps you!&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;kerry&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 12 Jan 2022 09:43:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/System-PLL-PFD-hardfault-error-while-booting-to-SDRAM/m-p/1398018#M17956</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-01-12T09:43:35Z</dc:date>
    </item>
  </channel>
</rss>

