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    <title>topic Re: in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Re/m-p/1356994#M16745</link>
    <description>&lt;P&gt;I included in my project (for MIMXRT1160-EVK) emWin GUI.&lt;/P&gt;&lt;P&gt;I get this error:&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;MIMXRT1166_EVK_CM4.axf section `NonCacheable' will not fit in region `SRAM_DTC_cm4' MIMXRT1166_EVK_CM4 C/C++ Problem&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;region `SRAM_DTC_cm4' overflowed by 7299032 bytes MIMXRT1166_EVK_CM4 C/C++ Problem&amp;nbsp;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;when I look at the code I see&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;#define APP_IMG_HEIGHT     1280
#define APP_IMG_WIDTH      720

AT_NONCACHEABLE_SECTION_ALIGN(static uint32_t s_frameBuffer[2][APP_IMG_HEIGHT][APP_IMG_WIDTH], FRAME_BUFFER_ALIGN);&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It's a huge amount of memory and can not fit into existent region.&lt;/P&gt;&lt;P&gt;What do I miss?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Actually it tries to put the buffer in&lt;/P&gt;&lt;P&gt;__attribute__((section("NonCacheable,\"aw\",%nobits @"))) static uint32_t s_frameBuffer[2][1280][720] __attribute__((aligned(64)))&lt;/P&gt;&lt;P&gt;And it's quite big&lt;/P&gt;&lt;P&gt;Memory region&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Used Size&amp;nbsp;&amp;nbsp; Region Size&amp;nbsp;&amp;nbsp;&amp;nbsp; %age Used&lt;BR /&gt;NCACHE_REGION: 0 GB&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp; 16 MB&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0.00%&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Why the compiler refers to SRAM_DTC_cm4 section?&lt;/P&gt;</description>
    <pubDate>Tue, 19 Oct 2021 08:10:15 GMT</pubDate>
    <dc:creator>john71</dc:creator>
    <dc:date>2021-10-19T08:10:15Z</dc:date>
    <item>
      <title>Re:</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Re/m-p/1356994#M16745</link>
      <description>&lt;P&gt;I included in my project (for MIMXRT1160-EVK) emWin GUI.&lt;/P&gt;&lt;P&gt;I get this error:&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;MIMXRT1166_EVK_CM4.axf section `NonCacheable' will not fit in region `SRAM_DTC_cm4' MIMXRT1166_EVK_CM4 C/C++ Problem&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;region `SRAM_DTC_cm4' overflowed by 7299032 bytes MIMXRT1166_EVK_CM4 C/C++ Problem&amp;nbsp;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;when I look at the code I see&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;#define APP_IMG_HEIGHT     1280
#define APP_IMG_WIDTH      720

AT_NONCACHEABLE_SECTION_ALIGN(static uint32_t s_frameBuffer[2][APP_IMG_HEIGHT][APP_IMG_WIDTH], FRAME_BUFFER_ALIGN);&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It's a huge amount of memory and can not fit into existent region.&lt;/P&gt;&lt;P&gt;What do I miss?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Actually it tries to put the buffer in&lt;/P&gt;&lt;P&gt;__attribute__((section("NonCacheable,\"aw\",%nobits @"))) static uint32_t s_frameBuffer[2][1280][720] __attribute__((aligned(64)))&lt;/P&gt;&lt;P&gt;And it's quite big&lt;/P&gt;&lt;P&gt;Memory region&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Used Size&amp;nbsp;&amp;nbsp; Region Size&amp;nbsp;&amp;nbsp;&amp;nbsp; %age Used&lt;BR /&gt;NCACHE_REGION: 0 GB&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp; 16 MB&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0.00%&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Why the compiler refers to SRAM_DTC_cm4 section?&lt;/P&gt;</description>
      <pubDate>Tue, 19 Oct 2021 08:10:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Re/m-p/1356994#M16745</guid>
      <dc:creator>john71</dc:creator>
      <dc:date>2021-10-19T08:10:15Z</dc:date>
    </item>
    <item>
      <title>Re: A region overflow problem.</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Re/m-p/1357629#M16759</link>
      <description>&lt;P&gt;So, the final question is - why I can not allocate the data in the section?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;__attribute__((section("NonCacheable,\"aw\",%nobits @"))) static uint32_t s_frameBuffer[2][1280][720] __attribute__((aligned(64)))&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Why I get&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;MIMXRT1166_EVK_CM4.axf section `NonCacheable' will not fit in region `SRAM_DTC_cm4' MIMXRT1166_EVK_CM4 C/C++ Problem&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;region `SRAM_DTC_cm4' overflowed by 7299032 bytes MIMXRT1166_EVK_CM4 C/C++ Problem&amp;nbsp;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Well...I looked at the example project. The generated linker file looks like&lt;/P&gt;&lt;P&gt;/* BSS section for NCACHE_REGION */&lt;BR /&gt;.bss_RAM2 : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;PROVIDE(__start_bss_RAM2 = .) ;&lt;BR /&gt;PROVIDE(__start_bss_NCACHE_REGION = .) ;&lt;BR /&gt;*(NonCacheable)&lt;BR /&gt;*(.bss.$RAM2)&lt;BR /&gt;*(.bss.$NCACHE_REGION)&lt;BR /&gt;*(.bss.$RAM2.*)&lt;BR /&gt;*(.bss.$NCACHE_REGION.*)&lt;BR /&gt;. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */&lt;BR /&gt;PROVIDE(__end_bss_RAM2 = .) ;&lt;BR /&gt;PROVIDE(__end_bss_NCACHE_REGION = .) ;&lt;BR /&gt;} &amp;gt; NCACHE_REGION AT&amp;gt; NCACHE_REGION&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;My one&lt;/P&gt;&lt;P&gt;/* BSS section for SRAM_ITC_cm4 */&lt;BR /&gt;.bss_RAM2 : ALIGN(4)&lt;BR /&gt;{&lt;BR /&gt;PROVIDE(__start_bss_RAM2 = .) ;&lt;BR /&gt;PROVIDE(__start_bss_SRAM_ITC_cm4 = .) ;&lt;BR /&gt;*(.bss.$RAM2)&lt;BR /&gt;*(.bss.$SRAM_ITC_cm4)&lt;BR /&gt;*(.bss.$RAM2.*)&lt;BR /&gt;*(.bss.$SRAM_ITC_cm4.*)&lt;BR /&gt;. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */&lt;BR /&gt;PROVIDE(__end_bss_RAM2 = .) ;&lt;BR /&gt;PROVIDE(__end_bss_SRAM_ITC_cm4 = .) ;&lt;BR /&gt;} &amp;gt; SRAM_ITC_cm4 AT&amp;gt; SRAM_ITC_cm4&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Where in the code I tie &lt;STRONG&gt;NonCacheable&lt;/STRONG&gt; to &lt;STRONG&gt;NCACHE_REGION&lt;/STRONG&gt; ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 19 Oct 2021 06:43:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Re/m-p/1357629#M16759</guid>
      <dc:creator>john71</dc:creator>
      <dc:date>2021-10-19T06:43:52Z</dc:date>
    </item>
    <item>
      <title>Re: A region overflow problem.</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Re/m-p/1357705#M16761</link>
      <description>&lt;P&gt;OK. I found it. It should be defined at Settings-&amp;gt;MCU Linker-&amp;gt;Managed Linker Script&lt;/P&gt;</description>
      <pubDate>Tue, 19 Oct 2021 07:39:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Re/m-p/1357705#M16761</guid>
      <dc:creator>john71</dc:creator>
      <dc:date>2021-10-19T07:39:34Z</dc:date>
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