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    <title>topic Re: Issue using enabled cache and TLS with iMXRT1051 in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1328000#M16000</link>
    <description>&lt;P&gt;Hello Karen,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The OCRAM is handled differently than the DTCM and ITCM memories. What happens if you &lt;SPAN&gt;place the mbedTLS into either the DTCM or ITCM?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Regards,&lt;BR /&gt;Victor &lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Mon, 23 Aug 2021 20:49:53 GMT</pubDate>
    <dc:creator>victorjimenez</dc:creator>
    <dc:date>2021-08-23T20:49:53Z</dc:date>
    <item>
      <title>Issue using enabled cache and TLS with iMXRT1051</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1323398#M15869</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am working on an MQTT round-trip test and I want to improve my performance, I tried enabling the D-Cache and the times improve with TCP port but when I tried with TLS the connection is lost, I read about the coherency problem, so I moved the mbedtls library into a non-cacheable region but the problem still present.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;</description>
      <pubDate>Fri, 13 Aug 2021 21:24:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1323398#M15869</guid>
      <dc:creator>KarenMczm</dc:creator>
      <dc:date>2021-08-13T21:24:40Z</dc:date>
    </item>
    <item>
      <title>Re: Issue using enabled cache and TLS with iMXRT1051</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1325614#M15931</link>
      <description>&lt;P&gt;Hello Karen,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In which memory specifically are you placing the &lt;SPAN&gt;mbedtls library?&amp;nbsp;To work with mbedTLS, you need to place the mbedTLS heap allocator in a non-cached memory that can be accessed by the DCP.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Also, you might find useful the following application note:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://www.nxp.com/docs/en/application-note/AN12042.pdf" target="_blank"&gt;Using the i.MXRT L1 Cache (nxp.com)&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Regards,&lt;BR /&gt;Victor&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 18 Aug 2021 16:55:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1325614#M15931</guid>
      <dc:creator>victorjimenez</dc:creator>
      <dc:date>2021-08-18T16:55:32Z</dc:date>
    </item>
    <item>
      <title>Re: Issue using enabled cache and TLS with iMXRT1051</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1325624#M15933</link>
      <description>&lt;P&gt;Thanks for the reply, I did the following changes in the code and the linker file to place mbedTLS into non-cached memory.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KarenMczm_0-1629306306622.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/153366iDA7813B5F27D35F4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KarenMczm_0-1629306306622.png" alt="KarenMczm_0-1629306306622.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KarenMczm_1-1629306317659.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/153367i9DFAF72A64D322E3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KarenMczm_1-1629306317659.png" alt="KarenMczm_1-1629306317659.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KarenMczm_2-1629306335779.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/153368i1B08D3233CF5E590/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KarenMczm_2-1629306335779.png" alt="KarenMczm_2-1629306335779.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KarenMczm_0-1629306515583.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/153370iB4AF968F8B069D9C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KarenMczm_0-1629306515583.png" alt="KarenMczm_0-1629306515583.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Karen&lt;/P&gt;</description>
      <pubDate>Wed, 18 Aug 2021 17:08:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1325624#M15933</guid>
      <dc:creator>KarenMczm</dc:creator>
      <dc:date>2021-08-18T17:08:46Z</dc:date>
    </item>
    <item>
      <title>Re: Issue using enabled cache and TLS with iMXRT1051</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1328000#M16000</link>
      <description>&lt;P&gt;Hello Karen,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The OCRAM is handled differently than the DTCM and ITCM memories. What happens if you &lt;SPAN&gt;place the mbedTLS into either the DTCM or ITCM?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Regards,&lt;BR /&gt;Victor &lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 23 Aug 2021 20:49:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1328000#M16000</guid>
      <dc:creator>victorjimenez</dc:creator>
      <dc:date>2021-08-23T20:49:53Z</dc:date>
    </item>
    <item>
      <title>Re: Issue using enabled cache and TLS with iMXRT1051</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1328003#M16001</link>
      <description>&lt;P&gt;Hi Victor,&lt;/P&gt;&lt;P&gt;I already solved the issue by moving the lwip library into the non-cacheable region as shown in the following image:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KarenMczm_0-1629752232577.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/153753i044D9CC48C604E79/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KarenMczm_0-1629752232577.png" alt="KarenMczm_0-1629752232577.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I tested with the mbedtls library in the non-cacheable region and outside of it. In both cases, it works, but if I put mbedtls in the non-cacheable region, the round trip using TLS is a bit slower than if I just leave lwip in the non-cacheable region.&lt;/P&gt;&lt;P&gt;Thanks for the support,&lt;/P&gt;&lt;P&gt;Karen&lt;/P&gt;</description>
      <pubDate>Mon, 23 Aug 2021 21:17:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Issue-using-enabled-cache-and-TLS-with-iMXRT1051/m-p/1328003#M16001</guid>
      <dc:creator>KarenMczm</dc:creator>
      <dc:date>2021-08-23T21:17:11Z</dc:date>
    </item>
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