i.MX RT Crossover MCUsのトピックRe: FlexSPI Cache Issue

FlexSPI Cache Issue

whermann — Mon, 19 Jul 2021 22:08:07 GMT

I have an i.MXRT1011 connected to an FPGA via QSPI using the FlexSPI module. I have the entire FPGA memory region configured as non-cacheable in the MPU, as I want any access to that region to cause an SPI transaction:

ARM_MPU_SetRegionEx(0, 0x61000000, ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64KB));

When attempting to access this memory region, I find that writes do consistently cause SPI transactions, but reads do not:

volatile uint8_t *fpgaReg = (volatile uint8_t *)(FPGA_AHB_START_ADDRESS + 0x2000); uint8_t rdVal = 0; *fpgaReg = (uint8_t)(i); // writes cause SPI transaction rdVal = *fpgaReg; // reads only cause an SPI transaction on first pass

I've tried both disabling the data cache, and invalidating the region I'm accessing before doing the read, but still no bus action. I figure I must be missing something about the CM7 cache but I'm not having any luck figuring it out.

Re: FlexSPI Cache Issue

jeremyzhou — Tue, 20 Jul 2021 02:46:20 GMT

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Actually, I'm a bit confused with your design, whether you use an FPGA to simulate the QSPI flash, if not, can you share the schematic of the custom board?
Looking forward to your reply.
Have a great day,
TIC

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Re: FlexSPI Cache Issue

whermann — Tue, 20 Jul 2021 03:25:08 GMT

The FPGA is acting more like a RAM than a flash device. FlexSPI port B1 is configured to communicate with the FPGA, using custom LUT entries to match the bus characteristics that I'm expecting on the FPGA side. I am only using AHB-accesses, no IP comms.

The transactions work properly (all of the FlexSPI parameters are set-up properly for both write and read accesses). The issue is that I can't reliably cause a read on the QSPI. Even though I have cache disabled for the FPGA's memory region, and even if I completely disable D-Cache, a read in software doesn't cause a read on the FlexSPI.

I appreciate your help with this issue.

Re: FlexSPI Cache Issue

jeremyzhou — Tue, 20 Jul 2021 10:23:17 GMT

Hi,
Thanks for your reply.
According to your reply, in your design, the FlexSPI port A connects the QSPI, meanwhile, the FlexSPI port B connects the FPGA.
In the application, you want to read and write the FPGA via AHB access mode, isn't my understanding right?
If yes, I was wondering if you can upload your demo code?
Have a great day,
TIC

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Re: FlexSPI Cache Issue

whermann — Wed, 21 Jul 2021 21:20:19 GMT

I figured out the issue. The FlexSPI module has the ability to check its own TX buffer for a cache hit when doing a read. Clearing the AHBCR[CACHABLEEN] bit disables this feature, so every AHB read from the FlexSPI memory space will cause a SPI transaction.

Re: FlexSPI Cache Issue

jingyangxie — Wed, 22 Jun 2022 07:45:10 GMT

Hi,

Could you share your config on flexspi?