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    <title>topic How can I tune QSPI? in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/How-can-I-tune-QSPI/m-p/826874#M1405</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm using RT1050 mcu with MT25QL512 of micron.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm working well to read and erase and write to flash with SDR mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And MT25QL512 supports DDR mode. so I changes&amp;nbsp;operation mode of flash from SDR to DDR&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But in DDR mode, it doesn't work to read ID of flash&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In SDR, I configure flexspi as below and it work well ( ID reads as 0x1020BA20)&lt;/P&gt;&lt;P&gt;flexspi_device_config_t deviceconfig = {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; .flexspiRootClk = 100000000,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; .flashSize = FLASH_SIZE,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ...&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24);&amp;nbsp;&amp;nbsp; /* Set PLL3 PFD0 clock 360MHZ. */&lt;BR /&gt;CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */&lt;BR /&gt;CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);&amp;nbsp;&amp;nbsp; /* flexspi clock 120M. */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;[4 * NOR_CMD_LUT_SEQ_IDX_READID] =&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),&lt;BR /&gt;&amp;nbsp;&amp;nbsp;[4 * NOR_CMD_LUT_SEQ_IDX_READID + 1] =&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In DDR, I configure flexspi as below and it doesn't work well ( ID reads as 0x04882E08)&lt;/P&gt;&lt;P&gt;flexspi_device_config_t deviceconfig = {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; .flexspiRootClk = 45000000,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; .flashSize = FLASH_SIZE,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ...&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24);&amp;nbsp;&amp;nbsp; /* Set PLL3 PFD0 clock 360MHZ. */&lt;BR /&gt;CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */&lt;BR /&gt;CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);&amp;nbsp;&amp;nbsp; /* flexspi clock 90M. */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;[4 * NOR_CMD_LUT_SEQ_IDX_READID] =&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_DDR, kFLEXSPI_1PAD, 0x04),&lt;BR /&gt;&amp;nbsp;&amp;nbsp;[4 * NOR_CMD_LUT_SEQ_IDX_READID + 1] =&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;How can I fix it?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 12 Nov 2018 10:16:40 GMT</pubDate>
    <dc:creator>yongjin2712_cho</dc:creator>
    <dc:date>2018-11-12T10:16:40Z</dc:date>
    <item>
      <title>How can I tune QSPI?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/How-can-I-tune-QSPI/m-p/826874#M1405</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm using RT1050 mcu with MT25QL512 of micron.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm working well to read and erase and write to flash with SDR mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And MT25QL512 supports DDR mode. so I changes&amp;nbsp;operation mode of flash from SDR to DDR&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But in DDR mode, it doesn't work to read ID of flash&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In SDR, I configure flexspi as below and it work well ( ID reads as 0x1020BA20)&lt;/P&gt;&lt;P&gt;flexspi_device_config_t deviceconfig = {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; .flexspiRootClk = 100000000,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; .flashSize = FLASH_SIZE,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ...&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24);&amp;nbsp;&amp;nbsp; /* Set PLL3 PFD0 clock 360MHZ. */&lt;BR /&gt;CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */&lt;BR /&gt;CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);&amp;nbsp;&amp;nbsp; /* flexspi clock 120M. */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;[4 * NOR_CMD_LUT_SEQ_IDX_READID] =&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),&lt;BR /&gt;&amp;nbsp;&amp;nbsp;[4 * NOR_CMD_LUT_SEQ_IDX_READID + 1] =&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In DDR, I configure flexspi as below and it doesn't work well ( ID reads as 0x04882E08)&lt;/P&gt;&lt;P&gt;flexspi_device_config_t deviceconfig = {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; .flexspiRootClk = 45000000,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; .flashSize = FLASH_SIZE,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ...&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24);&amp;nbsp;&amp;nbsp; /* Set PLL3 PFD0 clock 360MHZ. */&lt;BR /&gt;CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */&lt;BR /&gt;CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);&amp;nbsp;&amp;nbsp; /* flexspi clock 90M. */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;[4 * NOR_CMD_LUT_SEQ_IDX_READID] =&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_DDR, kFLEXSPI_1PAD, 0x04),&lt;BR /&gt;&amp;nbsp;&amp;nbsp;[4 * NOR_CMD_LUT_SEQ_IDX_READID + 1] =&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;How can I fix it?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Nov 2018 10:16:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/How-can-I-tune-QSPI/m-p/826874#M1405</guid>
      <dc:creator>yongjin2712_cho</dc:creator>
      <dc:date>2018-11-12T10:16:40Z</dc:date>
    </item>
    <item>
      <title>Re: How can I tune QSPI?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/How-can-I-tune-QSPI/m-p/826875#M1406</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Could you tell me if you set it to work in DTR mode?&lt;/P&gt;&lt;P&gt;Because I see that the memory needs to be configured for that, the Nonvolatile Configuration Register bit 5.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Aldo.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 21 Nov 2018 18:31:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/How-can-I-tune-QSPI/m-p/826875#M1406</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2018-11-21T18:31:02Z</dc:date>
    </item>
    <item>
      <title>Re: How can I tune QSPI?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/How-can-I-tune-QSPI/m-p/826876#M1407</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok, it needs some configuration to work in DTR mode as you said. So I'm trying to test it to set&amp;nbsp;fifth bit of enhanced volatile configuration register&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Nov 2018 15:56:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/How-can-I-tune-QSPI/m-p/826876#M1407</guid>
      <dc:creator>yongjin2712_cho</dc:creator>
      <dc:date>2018-11-27T15:56:18Z</dc:date>
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