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    <title>topic Re: 2 network interfaces with i.MX RT1060 in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825297#M1386</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hii..&lt;/P&gt;&lt;P&gt;&amp;nbsp;Can you please help me out to clear some point.&lt;/P&gt;&lt;P&gt;1. Can I use ENET0 and ENET1 simultaneously and how??&lt;/P&gt;&lt;P&gt;2. Is hardware support this if i have only one physical RJ45 connector??&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 20 Apr 2020 10:11:33 GMT</pubDate>
    <dc:creator>hemant_sharma</dc:creator>
    <dc:date>2020-04-20T10:11:33Z</dc:date>
    <item>
      <title>2 network interfaces with i.MX RT1060</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825292#M1381</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We consider using i.MX rt1060 instead of i.MX RT1050,&lt;/P&gt;&lt;P&gt;One of the reason is its multiple ethernet ports.&lt;/P&gt;&lt;P&gt;Yet, we see that its EVB comes with only one port. This means we can't verify connection on 2 ethernet ports.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are also not sure if the software freeRTOS/lwip and MCUXpresso SDK drivers , supports multiple network interfaces.&lt;/P&gt;&lt;P&gt;Does anyone knows if it is supported in the software package (SDK driver and lwip) ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;&lt;P&gt;ranran&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Oct 2018 15:02:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825292#M1381</guid>
      <dc:creator>rans</dc:creator>
      <dc:date>2018-10-04T15:02:16Z</dc:date>
    </item>
    <item>
      <title>Re: 2 network interfaces with i.MX RT1060</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825293#M1382</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ranran&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;both enet are supported (seems not simultaneously, using #if defined(ENET2))&lt;/P&gt;&lt;P&gt;in sdk and&amp;nbsp; AN12149&amp;nbsp; Implementing the IEEE 1588 V2 on i.MX RT Using PTPd, FreeRTOS,&lt;/P&gt;&lt;P&gt;and lwIP TCP/IP stack available on link&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060?tab=Documentation_Tab" title="https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060?tab=Documentation_Tab"&gt;i.MX RT1060 MCU/Applications Crossover Processor | Arm® Cortex®-M7 @600 MHz, 1MB SRAM |NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Oct 2018 23:49:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825293#M1382</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-10-04T23:49:52Z</dc:date>
    </item>
    <item>
      <title>Re: 2 network interfaces with i.MX RT1060</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825294#M1383</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In order to work with 2 emac simultaneously, I understand we need to modify sdk driver code.&lt;/P&gt;&lt;P&gt;Does Hadrware support&amp;nbsp;working with 2 emac&amp;nbsp;&lt;SPAN&gt;simultaneously&amp;nbsp;?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thank you,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;ranran&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Oct 2018 06:49:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825294#M1383</guid>
      <dc:creator>rans</dc:creator>
      <dc:date>2018-10-05T06:49:25Z</dc:date>
    </item>
    <item>
      <title>Re: 2 network interfaces with i.MX RT1060</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825295#M1384</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ranran&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes processor support it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Oct 2018 08:11:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825295#M1384</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-10-05T08:11:10Z</dc:date>
    </item>
    <item>
      <title>Re: 2 network interfaces with i.MX RT1060</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825296#M1385</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Reading sdk driver code, it seems that for imxrt106x&amp;nbsp;&lt;SPAN&gt;ENET2&amp;nbsp; is defined:&lt;/SPAN&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;#define ENET2&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ((ENET_Type *)ENET2_BASE)&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;I also find:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;err_t ethernetif1_init(struct netif *netif)&lt;BR /&gt;{&lt;BR /&gt; static struct ethernetif ethernetif_1;&lt;BR /&gt; ...&lt;/P&gt;&lt;P&gt;ethernetif_1.RxBuffDescrip = &amp;amp;(rxBuffDescrip_1[0]);&lt;BR /&gt; ...&lt;/P&gt;&lt;P&gt;return ethernetif_init(netif, &amp;amp;ethernetif_1, 1U, (ethernetif_config_t *)netif-&amp;gt;state);&lt;BR /&gt;}&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, I think the driver might already support working concurrently with 2 emacs.&lt;/P&gt;&lt;P&gt;Does it make sense ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;&lt;P&gt;ranran&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 07 Oct 2018 08:01:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825296#M1385</guid>
      <dc:creator>rans</dc:creator>
      <dc:date>2018-10-07T08:01:58Z</dc:date>
    </item>
    <item>
      <title>Re: 2 network interfaces with i.MX RT1060</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825297#M1386</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hii..&lt;/P&gt;&lt;P&gt;&amp;nbsp;Can you please help me out to clear some point.&lt;/P&gt;&lt;P&gt;1. Can I use ENET0 and ENET1 simultaneously and how??&lt;/P&gt;&lt;P&gt;2. Is hardware support this if i have only one physical RJ45 connector??&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Apr 2020 10:11:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/825297#M1386</guid>
      <dc:creator>hemant_sharma</dc:creator>
      <dc:date>2020-04-20T10:11:33Z</dc:date>
    </item>
    <item>
      <title>Re: 2 network interfaces with i.MX RT1060</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/1380727#M17384</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;have you found some solution?&lt;BR /&gt;In MCUXpresso nor ConfigTool I see no way to initialize the two ENET and ENET2 to work together, just pin configuration, but for example LWIP setting let me add just a single network interface "netif0" and not a second one..&lt;BR /&gt;Need support from NXP &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 02 Dec 2021 15:06:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/2-network-interfaces-with-i-MX-RT1060/m-p/1380727#M17384</guid>
      <dc:creator>simosilva</dc:creator>
      <dc:date>2021-12-02T15:06:20Z</dc:date>
    </item>
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