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    <title>topic LPSPI errors FreeRTOS in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-errors-FreeRTOS/m-p/1261490#M13780</link>
    <description>&lt;P&gt;I have a SPI client on LPSPI1 of my 1064 evk runnig FreeRTOS.&amp;nbsp;&amp;nbsp; Using the LPSPI_RTOS_transfer call I see no errors if I run only the task the transfer is performed in. If I enable two other tasks which communicate using LPUARTs (using EDMA) I see SPI errors.&amp;nbsp; None of the LPUART data is ever used on the SPI. I am trying to understand the driver. It looks like the tx Fifo is filled in the task and transfer is handled in LPSPI_MasterTransferHandleIRQ?&amp;nbsp;&amp;nbsp; I am not sure how the other tasks are effecting SPI.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Leroy&lt;/P&gt;</description>
    <pubDate>Tue, 13 Apr 2021 19:25:11 GMT</pubDate>
    <dc:creator>leroynash</dc:creator>
    <dc:date>2021-04-13T19:25:11Z</dc:date>
    <item>
      <title>LPSPI errors FreeRTOS</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-errors-FreeRTOS/m-p/1261490#M13780</link>
      <description>&lt;P&gt;I have a SPI client on LPSPI1 of my 1064 evk runnig FreeRTOS.&amp;nbsp;&amp;nbsp; Using the LPSPI_RTOS_transfer call I see no errors if I run only the task the transfer is performed in. If I enable two other tasks which communicate using LPUARTs (using EDMA) I see SPI errors.&amp;nbsp; None of the LPUART data is ever used on the SPI. I am trying to understand the driver. It looks like the tx Fifo is filled in the task and transfer is handled in LPSPI_MasterTransferHandleIRQ?&amp;nbsp;&amp;nbsp; I am not sure how the other tasks are effecting SPI.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Leroy&lt;/P&gt;</description>
      <pubDate>Tue, 13 Apr 2021 19:25:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-errors-FreeRTOS/m-p/1261490#M13780</guid>
      <dc:creator>leroynash</dc:creator>
      <dc:date>2021-04-13T19:25:11Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI errors FreeRTOS</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-errors-FreeRTOS/m-p/1262346#M13816</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/185292"&gt;@leroynash&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Can you let me know which errors are present in the SPI interface?&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The&amp;nbsp;LPSPI_RTOS_Transfer is an API that uses the same approach as the Non-Blocking example with the addition of using semaphores to control when the transfer is done. So it shouldn't block the UART communication.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Alexis Andalon&lt;/P&gt;</description>
      <pubDate>Thu, 15 Apr 2021 00:09:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-errors-FreeRTOS/m-p/1262346#M13816</guid>
      <dc:creator>Alexis_A</dc:creator>
      <dc:date>2021-04-15T00:09:17Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI errors FreeRTOS</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-errors-FreeRTOS/m-p/1269139#M13992</link>
      <description>&lt;P&gt;Our spi client was expecting a 50% SCLK cycle. When we looked at the bus we see that master can hold it off. We appear to always get he correct number of transitions per chip select when we remove this check. It is not ideal for bandwidth but at least it is now functioning.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Leroy&lt;/P&gt;</description>
      <pubDate>Tue, 27 Apr 2021 21:11:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-errors-FreeRTOS/m-p/1269139#M13992</guid>
      <dc:creator>leroynash</dc:creator>
      <dc:date>2021-04-27T21:11:54Z</dc:date>
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