<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX RT Crossover MCUsのトピックRe: RT1052 FlexRAM and JLink</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT1052-FlexRAM-and-JLink/m-p/821167#M1336</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Jordan&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;from log seems it needs some DTCM or ITCM, however since JLink&lt;/P&gt;&lt;P&gt;is developed and supported by segger proper way to post this on vendor support forum:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://wiki.segger.com/Main_Page" title="https://wiki.segger.com/Main_Page"&gt;SEGGER - Support Wiki&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 07 Aug 2018 23:11:40 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2018-08-07T23:11:40Z</dc:date>
    <item>
      <title>RT1052 FlexRAM and JLink</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT1052-FlexRAM-and-JLink/m-p/821166#M1335</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm configuring the FlexRAM on our chip to all 16 banks of OCRAM by writing to the IOMUXC_GPR registers in the startup code.&amp;nbsp; This successfully flashes over JLink and runs.&amp;nbsp; However, when trying to flash again, I must now hold reset on the device before JLink can download the new file.&amp;nbsp; What is causing this?&amp;nbsp; Does JLink need some DTCM or ITCM memory?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;JLink output:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Downloading file [./build/debug/image.hex]...&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;****** Error: Failed to prepare for programming.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Could not preserve target memory.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Error while determining flash info (Bank @ 0x60000000)&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Unspecified error -1&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Register writes:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;IOMUXC_GPR_GPR17 = 0x55555555&amp;nbsp; &amp;nbsp;// Set all banks to OCRAM&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;IOMUXC_GPR_GPR16 &amp;amp;= ~0x3&amp;nbsp; &amp;nbsp; // Disable ITCM and DTCM&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;IOMUXC_GPR_GPR16 |= 0x4&amp;nbsp; &amp;nbsp; //&amp;nbsp;Set FlexRAM Allocation to BankCfg&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Aug 2018 22:30:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT1052-FlexRAM-and-JLink/m-p/821166#M1335</guid>
      <dc:creator>jordanwagner</dc:creator>
      <dc:date>2018-08-03T22:30:50Z</dc:date>
    </item>
    <item>
      <title>Re: RT1052 FlexRAM and JLink</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT1052-FlexRAM-and-JLink/m-p/821167#M1336</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Jordan&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;from log seems it needs some DTCM or ITCM, however since JLink&lt;/P&gt;&lt;P&gt;is developed and supported by segger proper way to post this on vendor support forum:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://wiki.segger.com/Main_Page" title="https://wiki.segger.com/Main_Page"&gt;SEGGER - Support Wiki&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 07 Aug 2018 23:11:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT1052-FlexRAM-and-JLink/m-p/821167#M1336</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-08-07T23:11:40Z</dc:date>
    </item>
  </channel>
</rss>

