HyperRAM RWDS and FlexSPI DQS

patriciocohen — Fri, 12 Mar 2021 16:45:42 GMT

Hi guys,

I'm looking at the documentation of the FlexSPI and HyperRAM devices, and I don't understand the RWDS(DQS in the IMXRT) timing, when this signal is used as DATA MASK during the write transaction.

In the attached file JPG file, there are 2 pictures.

The top picture shows the write transaction signaling from hyperRAM's datasheet. The bottom picture shows the FlexSPI signaling for a HyperBus device, taken from IMXRT Ref Manual.

As you can see the RWDS signal is not aligned as shown in the in the HyperRAM's datasheet.
Is the RWDS being used as DATA MASK in the EVKs during write transactions or it is simple held at zero all times?

Thanks a lot

Patricio

Re: HyperRAM RWDS and FlexSPI DQS

jeremyzhou — Mon, 15 Mar 2021 03:16:07 GMT

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
In my opinion, the above two figures both show CK and Data are center-aligned, however, in the below figure, the RWDS shift a half-cycle phase versus the above figure.
About using the HyperRAM with the i.MX RT, to provide the fastest possible support, I'd highly recommend you refer to the application note and its corresponding code.
corresponding code.
Have a great day,
TIC

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topic HyperRAM RWDS and FlexSPI DQS in i.MX RT Crossover MCUs

HyperRAM RWDS and FlexSPI DQS

Re: HyperRAM RWDS and FlexSPI DQS