topic Re: cache in i.MX RT Crossover MCUs

cache

zhangyanming — Fri, 30 Nov 2018 01:26:07 GMT

Lately, i use i.MX RT1052 to develpe a product, i use cache to improve performance.But when i use the speed_test() function to test the cache performance,the code is executed in ITCM,i find that when i enable D-cache with the adram (0x80000000,2MB)memory default configuration cacheable/WT(no WA),the speed is the faster than i disable the cache.According to my understanding,WT is a write updates both the cache and the external memory system,enable and disable the cache does not affect data access speed,so why?when i enable the D-cache,i configure the adram (0x80000000,2MB)memory cache/WB(no WA),i find the cache/WT(no WA) and cache/WB(no WA) speed is same.so why?

uint32_t AudioInData = 0;
void speed_test(void)
{
      uint32_t i = 0 , j = 0;
      for(i=0;i<30000;i++)
      {
            for(j=0;j<30000;j++)
            {
                  AudioInData += 0xA5A5;
            }
      }
}

,

Re: cache

Yuri — Mon, 03 Dec 2018 07:10:44 GMT

Hello,

Do You use the recent SDK (2.4.2) for i.MX RT1050?

Welcome | MCUXpresso SDK Builder

Use function BOARD_ConfigMPU() in file board.c for memory configuring.

Have a great day,

Yuri

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