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    <title>topic TCM &amp;amp; Cache... in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/TCM-amp-Cache/m-p/1227256#M12591</link>
    <description>&lt;P&gt;I'm working on a new feature (SPEEX echo cancellation) for my hardware that, as of right now, is not working because of what appears to be not-enough-horsepower in the '1062.&amp;nbsp; Its still pretty early, so its possible (i.e. likely) I just have a problem with how I'm using the echo canceller, but it raises a general question that I'm sure has already been answered somewhere regarding optimization...&lt;/P&gt;&lt;P&gt;I have text and data mapped to ITCM and DTCM respectively, so does it matter how I have cache configured (MPU) for those areas? Is cache even in the picture when using TCM?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;tx&lt;/P&gt;&lt;P&gt;Ed&lt;/P&gt;</description>
    <pubDate>Fri, 05 Feb 2021 16:31:46 GMT</pubDate>
    <dc:creator>EdSutter</dc:creator>
    <dc:date>2021-02-05T16:31:46Z</dc:date>
    <item>
      <title>TCM &amp; Cache...</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/TCM-amp-Cache/m-p/1227256#M12591</link>
      <description>&lt;P&gt;I'm working on a new feature (SPEEX echo cancellation) for my hardware that, as of right now, is not working because of what appears to be not-enough-horsepower in the '1062.&amp;nbsp; Its still pretty early, so its possible (i.e. likely) I just have a problem with how I'm using the echo canceller, but it raises a general question that I'm sure has already been answered somewhere regarding optimization...&lt;/P&gt;&lt;P&gt;I have text and data mapped to ITCM and DTCM respectively, so does it matter how I have cache configured (MPU) for those areas? Is cache even in the picture when using TCM?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;tx&lt;/P&gt;&lt;P&gt;Ed&lt;/P&gt;</description>
      <pubDate>Fri, 05 Feb 2021 16:31:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/TCM-amp-Cache/m-p/1227256#M12591</guid>
      <dc:creator>EdSutter</dc:creator>
      <dc:date>2021-02-05T16:31:46Z</dc:date>
    </item>
    <item>
      <title>Re: TCM &amp; Cache...</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/TCM-amp-Cache/m-p/1227311#M12593</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;The tightly coupled memeries operate at core speed without wait states and are not cacheable.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 05 Feb 2021 18:27:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/TCM-amp-Cache/m-p/1227311#M12593</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2021-02-05T18:27:21Z</dc:date>
    </item>
    <item>
      <title>Re: TCM &amp; Cache...</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/TCM-amp-Cache/m-p/1227314#M12594</link>
      <description>&lt;P&gt;That's what I thought...&lt;/P&gt;&lt;P&gt;Thanks Mark&lt;/P&gt;</description>
      <pubDate>Fri, 05 Feb 2021 18:30:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/TCM-amp-Cache/m-p/1227314#M12594</guid>
      <dc:creator>EdSutter</dc:creator>
      <dc:date>2021-02-05T18:30:02Z</dc:date>
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