RT105x boot from QSPI(W25Q256JV)

Jeannie — Tue, 27 Oct 2020 01:57:04 GMT

Hello. My design Board use RT1052 for main controller and boot from QSPI flash (W25Q256JV). W25Q256JV data sheet as follow link:

https://www.winbond.com/resource-files/w25q256jv%20spi%20revg%2008032017.pdf

The follow text is copy from "fsl_flexspi_nor_flash.c".

My question is how to modify document "fsl_flexspi_nor_flash.c" according to W25Q256JV (Data sheet as follow link):

const flexspi_nor_config_t hyperflash_config =
{
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClksrc=kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.columnAddressWidth = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.controllerMiscOption = (1u << kFlexSpiMiscOffset_DdrModeEnable) |
(1u << kFlexSpiMiscOffset_WordAddressableEnable) |
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) |
(1u << kFlexSpiMiscOffset_DiffClkEnable),
.sflashPadType = kSerialFlash_8Pads,
.serialClkFreq = kFlexSpiSerialClk_133MHz,
.sflashA1Size = 64u * 1024u * 1024u,
.dataValidTime = {16u, 16u},
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
},
},
.pageSize = 512u,
.sectorSize = 256u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = true,
};

Re: RT105x boot from QSPI(W25Q256JV)

mjbcswitzerland — Tue, 27 Oct 2020 11:08:43 GMT

For the W25Q16 the following changes are needed

csHoldTime = 1u,
.csSetupTime = 2u,
.columnAddressWidth = 0u,

.controllerMiscOption = 0,

.sflashPadType = kSerialFlash_4Pads,

.dataValidTime = {0u, 0u},

.pageSize = 256u,
.sectorSize = 4u * 1024u,

.isUniformBlockSize = false,

.sflashA1Size = 2u * 1024u * 1024u,

You can also look at a reference for the 1064's internal W25Q or from the Teensy 4 project where the W25Q16 and/or 64 are used.

The LUTs that I use for this part are as follows but uses a different method to the one that the NXP config uses - although the content should be understandable:

// Read LUT
//
FLEXSPI_LUT_1PAD_SEQ_1(FLEXSPI_Command_SDR, FAST_READ_QUAD_I_O) | FLEXSPI_LUT_4PAD_SEQ_2(FLEXSPI_Command_RADDR_SDR, ADDRESS_LENGTH_24BITS),
FLEXSPI_LUT_4PAD_SEQ_1(FLEXSPI_Command_DUMMY_SDR, 0x06) | FLEXSPI_LUT_4PAD_SEQ_2(FLEXSPI_Command_READ_SDR, 0x04),
0,0,
// Read status register
//
FLEXSPI_LUT_1PAD_SEQ_1(FLEXSPI_Command_SDR, READ_STATUS_REGISTER_1) | FLEXSPI_LUT_1PAD_SEQ_2(FLEXSPI_Command_READ_SDR, 0x04),
0,0,0,

0,0,0,0,

// Write enable
//
FLEXSPI_LUT_1PAD_SEQ_1(FLEXSPI_Command_SDR, WRITE_ENABLE) | FLEXSPI_LUT_1PAD_SEQ_2(FLEXSPI_Command_STOP, 0x00),
0,0,0,

0,0,0,0,

// Sub-sector erase
//
FLEXSPI_LUT_1PAD_SEQ_1(FLEXSPI_Command_SDR, SUB_SECTOR_ERASE) | FLEXSPI_LUT_1PAD_SEQ_2(FLEXSPI_Command_RADDR_SDR, ADDRESS_LENGTH_24BITS),
0,0,0,

0,0,0,0,

// Block erase
//
FLEXSPI_LUT_1PAD_SEQ_1(FLEXSPI_Command_SDR, BLOCK_ERASE) | FLEXSPI_LUT_1PAD_SEQ_2(FLEXSPI_Command_RADDR_SDR, ADDRESS_LENGTH_24BITS),
0,0,0,

// Page program
//
FLEXSPI_LUT_1PAD_SEQ_1(FLEXSPI_Command_SDR, PAGE_PROG) | FLEXSPI_LUT_1PAD_SEQ_2(FLEXSPI_Command_RADDR_SDR, ADDRESS_LENGTH_24BITS),
FLEXSPI_LUT_1PAD_SEQ_1(FLEXSPI_Command_WRITE_SDR, 0x04) | FLEXSPI_LUT_1PAD_SEQ_2(FLEXSPI_Command_STOP, 0x00),
0,0,

0,0,0,0,

// Chip erase
//
FLEXSPI_LUT_1PAD_SEQ_1(FLEXSPI_Command_SDR, CHIP_ERASE) | FLEXSPI_LUT_1PAD_SEQ_2(FLEXSPI_Command_STOP, 0x00),
0,0,0,

0,0,0,0,
0,0,0,0,
0,0,0,0,
0,0,0,0,

The complication with your W25Q256 is that it needs t use 4 byte addressing mode to be able to address its complete content. This means that either the chip's 4 byte mode needs to be programmed beforehand so that it boots in that mode or else it needs to be changed by writing the mode during operation and before the extended addressing is used (the second method is probably preferred).

For booting the W25Q16 scripts should be OK as long as you later change the mode to 4 byte and also reconfigure the LUTs to their 4 byte addressing versions before using the complete chip's content.

Regards

Mark
[uTasker project developer for Kinetis and i.MX RT]
Contact me by personal message or on the uTasker web site to discuss professional training, solutions to problems or product development requirements

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