dcp hash context alignment

michalhojsik — Thu, 08 Oct 2020 19:08:38 GMT

Hi.

I have a question related to the DCP driver from SDK2.8.2 (SDK_2.8.2_EVK-MIMXRT1060\devices\MIMXRT1062\drivers\fsl_dcp.c).

The function DCP_HASH_Update(...) calls dcp_hash_check_context(...), which (with DCP_USE_DCACHE=1) checks that the input hash context is 32-byte aligned.

I would like to ask: Why is this check performed?

As far as I understand the documentation (i.MX RT 1050 security reference manual, Rev. 1, 04/2018, section 7.4.6 DCP context buffer pointer), there isn't any requirement for the context alignment. It only states, that it should be word-aligned for optimal performance. There is no requirement for 32-byte alignment.

Thank you.

Regards,

Michal

Re: dcp hash context alignment

FelipeGarcia — Mon, 12 Oct 2020 21:24:16 GMT

Hello Michal,

This is a DCACHE limitation. As you can see in the following application note, the buffer address should be L1 cache line size aligned (32 bytes in i.MXRT). Therefore, when using DCACHE 32-byte alignment is required.

https://www.nxp.com/docs/en/application-note/AN12042.pdf

Best regards,

Felipe

topic dcp hash context alignment in i.MX RT Crossover MCUs

dcp hash context alignment

Re: dcp hash context alignment