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    <title>topic Re: FlexPWM clarifications for i.MXRT 106x in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexPWM-clarifications-for-i-MXRT-106x/m-p/1151376#M10042</link>
    <description>&lt;P&gt;Hi Hugo,&lt;/P&gt;
&lt;P&gt;1. Please see page 301 in table 10-1, there is&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;FLEXPWM1_PWM0_X and&amp;nbsp;&amp;nbsp;FLEXPWM1_PWM1_X.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;2. Yes, all FlexPWM fault signal is from XBAR1. XBAR1 is main XBAR. XBAR2 and XBAR3 are used to do logical operation.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;3. Do you mean SMxDISMAP0 and SMxDISMAP1? I think SMxDISMAP1 is for fault channel1. But RT106x FlexPWM hasn't fault channel1.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Jing&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 10 Sep 2020 06:59:10 GMT</pubDate>
    <dc:creator>jingpan</dc:creator>
    <dc:date>2020-09-10T06:59:10Z</dc:date>
    <item>
      <title>FlexPWM clarifications for i.MXRT 106x</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexPWM-clarifications-for-i-MXRT-106x/m-p/1150981#M10033</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;After reading the reference manual for i.MX RT 1060 concerning the FlexPWM modules, there is still few things that are unclear to me:&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;1.&lt;/STRONG&gt;&lt;BR /&gt;The reference manual says that that only FlexPWM1 has PWM_X outputs for each submodules. However, in MCUXpresso pins configurations interface, it seems that only FLEXPWM1_PWMX2 and FLEXPWM1_PWMX3 can be mapped. Am I missing something?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;2.&lt;BR /&gt;&lt;/STRONG&gt;Each PWM has 4 fault inputs. However, they are listed in the XBAR1 output assignments ? Shouldn't they be listed in XBARx input assignments ?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;3.&lt;BR /&gt;&lt;/STRONG&gt;There is two registers to enable/disable the 4 fault inputs for each submodules. This means that there is 2 bits (one in each register) to enable/disable 1 fault intput. Why is there 2 registers then?&lt;/P&gt;&lt;P&gt;Thanks,&lt;BR /&gt;Hugo&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 09 Sep 2020 09:00:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexPWM-clarifications-for-i-MXRT-106x/m-p/1150981#M10033</guid>
      <dc:creator>h_bouchard</dc:creator>
      <dc:date>2020-09-09T09:00:22Z</dc:date>
    </item>
    <item>
      <title>Re: FlexPWM clarifications for i.MXRT 106x</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexPWM-clarifications-for-i-MXRT-106x/m-p/1151376#M10042</link>
      <description>&lt;P&gt;Hi Hugo,&lt;/P&gt;
&lt;P&gt;1. Please see page 301 in table 10-1, there is&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;FLEXPWM1_PWM0_X and&amp;nbsp;&amp;nbsp;FLEXPWM1_PWM1_X.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;2. Yes, all FlexPWM fault signal is from XBAR1. XBAR1 is main XBAR. XBAR2 and XBAR3 are used to do logical operation.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;3. Do you mean SMxDISMAP0 and SMxDISMAP1? I think SMxDISMAP1 is for fault channel1. But RT106x FlexPWM hasn't fault channel1.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Jing&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 10 Sep 2020 06:59:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexPWM-clarifications-for-i-MXRT-106x/m-p/1151376#M10042</guid>
      <dc:creator>jingpan</dc:creator>
      <dc:date>2020-09-10T06:59:10Z</dc:date>
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