i.MX SolutionsのトピックI.MX6Q EIM bus Clock Problem https://community.nxp.com/t5/i-MX-Solutions/I-MX6Q-EIM-bus-Clock-Problem/m-p/1944795#M508 <P>The iMX6Q chip uses the EIM bus to communicate with the FPGA. When choosing asynchronous communication, the SignalTap of QuartusII software is used on the FPGA side to capture CS, OE, and RW signals. The effective duration of CS signals is not fixed. The device configuration is shown in the following figure</P> Sat, 31 Aug 2024 08:57:50 GMT 郑焰秋 2024-08-31T08:57:50Z I.MX6Q EIM bus Clock Problem https://community.nxp.com/t5/i-MX-Solutions/I-MX6Q-EIM-bus-Clock-Problem/m-p/1944795#M508 <P>The iMX6Q chip uses the EIM bus to communicate with the FPGA. When choosing asynchronous communication, the SignalTap of QuartusII software is used on the FPGA side to capture CS, OE, and RW signals. The effective duration of CS signals is not fixed. The device configuration is shown in the following figure</P> Sat, 31 Aug 2024 08:57:50 GMT https://community.nxp.com/t5/i-MX-Solutions/I-MX6Q-EIM-bus-Clock-Problem/m-p/1944795#M508 郑焰秋 2024-08-31T08:57:50Z