<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: Question, i.MX6Quad power-on sequence</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6Quad-power-on-sequence/m-p/652354#M99809</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes such power-up sequence is allowed, note VDD_SNVS_IN supply must be&lt;/P&gt;&lt;P&gt;turned on before any other power supply and it may be connected (shorted) with VDD_HIGH_IN supply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Mar 2017 05:52:17 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-03-15T05:52:17Z</dc:date>
    <item>
      <title>Question, i.MX6Quad power-on sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6Quad-power-on-sequence/m-p/652353#M99808</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about power-on sequence for i.MX6Q.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;After reading chapter 4 in your Hardware Development Guide for i.MX6Quad, my customer wants to know whether the following sequence, in the following order, can be allowed.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- &amp;nbsp;2.8V(VDDHIGH_IN) and 1.2V(NVCC_RGMII) are turned on simultaneously.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-&amp;nbsp; Then, 3.3V(NVCC_EIM0~2,NVCC_ENET,NVCC_GPIO,NVCC_SD3,NVCC_NANDF,NVCC_JTAG) and 2.5V(NVCC_CSI,NVCC_SD1,NVCC_SD2) are turned on simultaneously.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-&amp;nbsp; Then, NVCC_DRAM(1.5V) is turned on.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could you show me whether the above is allowed?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Mar 2017 03:34:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6Quad-power-on-sequence/m-p/652353#M99808</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2017-03-15T03:34:27Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX6Quad power-on sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6Quad-power-on-sequence/m-p/652354#M99809</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes such power-up sequence is allowed, note VDD_SNVS_IN supply must be&lt;/P&gt;&lt;P&gt;turned on before any other power supply and it may be connected (shorted) with VDD_HIGH_IN supply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Mar 2017 05:52:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX6Quad-power-on-sequence/m-p/652354#M99809</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-03-15T05:52:17Z</dc:date>
    </item>
  </channel>
</rss>

