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    <title>i.MX ProcessorsのトピックRe: i.MX6 PCIe read hang</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651304#M99634</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi JBD&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for explanation of these parameters one can refer to PCIe specifications&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://pcisig.com/specifications" title="https://pcisig.com/specifications"&gt;Specifications | PCI-SIG&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Mar 2017 11:31:20 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-03-15T11:31:20Z</dc:date>
    <item>
      <title>i.MX6 PCIe read hang</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651301#M99631</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We designed a custom board based on imx6Dual, where it connects Intel i210 ethernet controller through PCIexpress.&lt;/P&gt;&lt;P&gt;We are using linux kernel 4.1.15_1.0.0 retrieved from Yocto BSP.&lt;/P&gt;&lt;P&gt;Intel IGB driver correctly identifies i210 component through PCIexpress, but linux hangs randomly (and quickly : ~ 1 to 10secs after the beginning of i210 initialization).&lt;/P&gt;&lt;P&gt;I added printk in every beginning and ending of pcie-imx6.c functions and igb functions, and it appears that it hangs at a read on a register : "value = readl(&amp;amp;hw_addr[reg]);" in "igb_rd32(struct e1000_hw *hw, u32 reg)" in "igb_main.c".&lt;/P&gt;&lt;P&gt;We searched for similar issue on imx6 pcie and it seems that imx6 pcie has some dysfunctions.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I found that PCIe PHY Tx values can be adjusted by IOMUXC_GPR8 register, depending on the hardware, but there is no clue for this. Are these values criticals and can they produce read hang ?&lt;/P&gt;&lt;P&gt;Is there any documentation on PHY Tx adjustements and explanations ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In advance thank you for your support.&lt;/P&gt;&lt;P&gt;Any suggestions will be appreciated !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;JBD.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Mar 2017 18:39:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651301#M99631</guid>
      <dc:creator>jbd64</dc:creator>
      <dc:date>2017-03-14T18:39:34Z</dc:date>
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    <item>
      <title>Re: i.MX6 PCIe read hang</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651302#M99632</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi JBD&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for IOMUXC_GPR8&amp;nbsp; usage please check AN4784 PCIe Certification Guide for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite&lt;BR /&gt;&lt;A class="link-titled" href="http://www.nxp.com/assets/documents/data/en/application-notes/AN4784.pdf" title="http://www.nxp.com/assets/documents/data/en/application-notes/AN4784.pdf"&gt;http://www.nxp.com/assets/documents/data/en/application-notes/AN4784.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Mar 2017 23:24:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651302#M99632</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-03-14T23:24:07Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 PCIe read hang</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651303#M99633</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor, &lt;/P&gt;&lt;P&gt;Thank you for your response, I appreciate it !&lt;/P&gt;&lt;P&gt;I already read AN4784 document, but it did not help us a lot since we don't have the mandatory measure equipment to process the test.&lt;/P&gt;&lt;P&gt;We can not find any explanation on how to configure IOMUXC_GPR8 fields without following AN4784 procedure, which is very cost effective when you don't already own the measure equipment.&lt;/P&gt;&lt;P&gt;Can you explain us how each field of IOMUXC_GPR8 modifies PHY Tx timings/levels; i.e. :&lt;/P&gt;&lt;P&gt;- What is the launch amplitude of the transmitter and how TX_SWING_LOW modifies it ?&lt;/P&gt;&lt;P&gt;- What is the Tx driver SWING_FULL value ?&lt;/P&gt;&lt;P&gt;- What is the Tx driver de-emphasis value ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you are not able to reply to it, can you at least redirect me to a document in order to dig into it ? (subsection of pcie specification or else...).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your support.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;JBD.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Mar 2017 09:25:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651303#M99633</guid>
      <dc:creator>jbd64</dc:creator>
      <dc:date>2017-03-15T09:25:10Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 PCIe read hang</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651304#M99634</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi JBD&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for explanation of these parameters one can refer to PCIe specifications&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://pcisig.com/specifications" title="https://pcisig.com/specifications"&gt;Specifications | PCI-SIG&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Mar 2017 11:31:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651304#M99634</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-03-15T11:31:20Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 PCIe read hang</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651305#M99635</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Thank you for your link, but our organization is not member of PCI-SIG.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Mar 2017 08:56:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-PCIe-read-hang/m-p/651305#M99635</guid>
      <dc:creator>jbd64</dc:creator>
      <dc:date>2017-03-17T08:56:13Z</dc:date>
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