topic Re: PCI Express PLL cannot lock on about 5% of all IMX7D CPUs. in i.MX Processors

PCI Express PLL cannot lock on about 5% of all IMX7D CPUs.

leonidsegal — Tue, 14 Mar 2017 14:36:25 GMT

Hello,

We assembled a large number of CPUs on our cards and in about 5% of them the PCI Express PLL cannot lock.

The issue can be solved by raising the 1.0V LDO to about 1.05V in part of the CPUs (this is the maximum working condition). And in part of them the voltage should be raised to 1.1V for PLL lock.

Is this a known issue?

Thank you.

Re: PCI Express PLL cannot lock on about 5% of all IMX7D CPUs.

igorpadykov — Wed, 15 Mar 2017 00:01:34 GMT

Hi Leonid

reason may be board noise, please check that C458 & C459 are removed.

Schematics (2)
Design files for i.MX 7Dual (REV D)
Design files, including hardware schematics, Gerbers, and OrCAD files for i.MX 7Dual (REV D)
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors/i.mx-7-processors/i.mx-7dual-processors-heterogeneous-processing-with-dual-arm-cortex-a7-cores-and-cortex-m4-core:i.MX7D?fpsp=1&tab=Design_Tools_Tab

also one can check

PCIe link doesn't come up with XIO2001 PCI bridge on iMX6Q custom board

Best regards
igor
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Re: PCI Express PLL cannot lock on about 5% of all IMX7D CPUs.

leonidsegal — Wed, 15 Mar 2017 11:02:40 GMT

Hello,

Yes the capacitors are replaced with 0R resistors.

The issue is that the initialization process fails before accessing the RESET GPIO pins.

The function that fails is:

static void pci_imx_phy_pll_locked(struct imx6_pcie *imx6_pcie){
   u32 val;
   int count = 20000;
   while (count--) {
      regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
      if (val & BIT(31))
         break;
      udelay(10);
      if (count == 0)
         pr_info("pcie phy pll can't be locked.\n");
   }
}

We inspected the voltage on pins AA9, AA10, AA11, AA12 it seems to be ok.

The problem is very consistent on part of the boards:

if one board is working it is 100% working, tested in 100 power ups
If it fails then it fails, until the imx6_pcie->pcie_phy_regulator is not set to a higher level in this section:

static void imx6_pcie_init_phy(struct pcie_port *pp){
   int ret;
   struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
   if (is_imx7d_pcie(imx6_pcie)) {
      /* Enable PCIe PHY 1P0D */
      regulator_set_voltage(imx6_pcie->pcie_phy_regulator,1000000, 1000000);
      ret = regulator_enable(imx6_pcie->pcie_phy_regulator);
      if (ret)
         dev_err(pp->dev, "failed to enable pcie regulator.\n");
      /* pcie phy ref clock select; 1? internal pll : external osc */
      regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,BIT(5), imx6_pcie->phy_refclk ? BIT(5) : 0);
      /* get pcie phy out of reset to get correct clock rate */
      regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(1), 0);
      regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(2), 0);
      regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(6), 0);
      ...

If the bold value is changed to 1100000 than all boards are working. But 1.1V is out of spec...

Re: PCI Express PLL cannot lock on about 5% of all IMX7D CPUs.

igorpadykov — Wed, 15 Mar 2017 11:45:49 GMT

is PCIe working in uboot, may be useful

git.denx.de Git - u-boot.git/commitdiff

~igor

Re: PCI Express PLL cannot lock on about 5% of all IMX7D CPUs.

leonidsegal — Thu, 16 Mar 2017 09:05:46 GMT

I could not find any uboot release that supports PCI on mx7...

Re: PCI Express PLL cannot lock on about 5% of all IMX7D CPUs.

igorpadykov — Thu, 16 Mar 2017 10:36:52 GMT

general way for such issues is to follow procedure described in AN5158

PCI Express® Certification Guide for the i.MX 6SoloX

http://www.nxp.com/assets/documents/data/en/application-notes/AN5158.pdf

Best regards
igor