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    <title>topic Re: Where DDR Ram gets initialised when there is no SPL  in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Where-DDR-Ram-gets-initialised-when-there-is-no-SPL/m-p/650260#M99489</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Other mechanism for system initialization is using the DCD Table.&lt;/P&gt;&lt;P class=""&gt;Please refer to &lt;SPAN class=""&gt;Chapter 1 (Porting U-Boot from an i.MX 6/7 Reference &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Board to an i.MX 6/7 Custom Board) of “i.MX_BSP_Porting_Guide.pdf” &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;in Linux documentation.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0-LINUX-DOCS&amp;amp;Parent_nodeId=1337699481071706174845&amp;amp;Parent_pageType=product" title="http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0-LINUX-DOCS&amp;amp;Parent_nodeId=1337699481071706174845&amp;amp;Parent_pageType=product"&gt;http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0-LINUX-DOCS&amp;amp;Parent_nodeId=1337699481071706174845&amp;amp;Parent_pageType…&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 05 Apr 2017 11:16:40 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2017-04-05T11:16:40Z</dc:date>
    <item>
      <title>Where DDR Ram gets initialised when there is no SPL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Where-DDR-Ram-gets-initialised-when-there-is-no-SPL/m-p/650259#M99488</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The normal boot process is , SPL is&amp;nbsp;loaded&amp;nbsp;to the SRAM&amp;nbsp;and during the execution of the SPL&amp;nbsp;&amp;nbsp;DDR Ram gets initialized.&lt;/P&gt;&lt;P&gt;Once the DDR is initialized , u-boot /kernel&amp;nbsp; is loaded to DDR Ram.&lt;/P&gt;&lt;P&gt;Now SPL is no longer in use and CPU directly loads the u-boot to DRAM. Now question is , where the DDR Ram gets initialized ?&amp;nbsp; IMX can load u-boot only when the DDR ram is initialized. Where this initialization happens ?&lt;/P&gt;&lt;P&gt;Please suggest.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Aditya Nagal&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Apr 2017 11:09:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Where-DDR-Ram-gets-initialised-when-there-is-no-SPL/m-p/650259#M99488</guid>
      <dc:creator>adityanagal</dc:creator>
      <dc:date>2017-04-05T11:09:04Z</dc:date>
    </item>
    <item>
      <title>Re: Where DDR Ram gets initialised when there is no SPL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Where-DDR-Ram-gets-initialised-when-there-is-no-SPL/m-p/650260#M99489</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Other mechanism for system initialization is using the DCD Table.&lt;/P&gt;&lt;P class=""&gt;Please refer to &lt;SPAN class=""&gt;Chapter 1 (Porting U-Boot from an i.MX 6/7 Reference &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Board to an i.MX 6/7 Custom Board) of “i.MX_BSP_Porting_Guide.pdf” &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;in Linux documentation.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0-LINUX-DOCS&amp;amp;Parent_nodeId=1337699481071706174845&amp;amp;Parent_pageType=product" title="http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0-LINUX-DOCS&amp;amp;Parent_nodeId=1337699481071706174845&amp;amp;Parent_pageType=product"&gt;http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0-LINUX-DOCS&amp;amp;Parent_nodeId=1337699481071706174845&amp;amp;Parent_pageType…&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Apr 2017 11:16:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Where-DDR-Ram-gets-initialised-when-there-is-no-SPL/m-p/650260#M99489</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-04-05T11:16:40Z</dc:date>
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