i.MX ProcessorsのトピックRe: Sharing a GPIO bank between A9 and M4 in i.MX6SX

Sharing a GPIO bank between A9 and M4 in i.MX6SX

Balaji_ng — Sun, 25 Sep 2016 04:55:44 GMT

Can I share a different GPIO pins belonging to same GPIO bank between A9 and M4 in i.MX6SoloX? For example, Can I use GPIO Pin-0 of GPIO Bank-3 in M4 and GPIO Pin-1 of GPIO Bank-3 in A9?

Regards

Balaji.V

Re: Sharing a GPIO bank between A9 and M4 in i.MX6SX

igorpadykov — Sun, 25 Sep 2016 23:28:36 GMT

Hi Balaji

only whole GPIO module can be shared, not particular GPIO bits,

please look at description of RDC in Chapter 52 Resource Domain Controller (RDC)

i.MX6SX Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf

Best regards
igor
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Re: Sharing a GPIO bank between A9 and M4 in i.MX6SX

Balaji_ng — Mon, 26 Sep 2016 09:55:28 GMT

But my exercise is proving otherwise.

Let me explain my setup.

1. I have a i.MX6SoloX SDB.

In M4:

1. Configured 5 GPIOs as outputs. (GPIO3.20, GPIO3.21, GPIO3.22, GPIO3.23, GPIO3.24).

2. Configured 1 GPIO as input (GPIO3.27).

3. In a while loop, I am toggling the 5 output GPIOs, scan the Input GPIO and print its state.

In A9:

1. I am using imx6sx-sdb-m4.dts.

2. In imx6sx-sdb.dtsi, added the 16 GPIOs entries (corresponding to GPIO3.1 to GPIO3.16) in the pinctrl_hog group. Below is a snippet of this file.

&iomuxc {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>;

 imx6x-sdb {
 pinctrl_hog: hoggrp {
 fsl,pins = <
 MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
 MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
 MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059

 MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x17059
 MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x17059
 MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x17059
 MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x17059
 MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x17059
 MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x17059
 MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x17059
 MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x17059
 MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x17059
 MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x17059
 MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x17059
 MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x17059
 MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x17059
 MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x17059
 MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x17059
 MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x17059
 MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x17059
 >;
 };

3. Script that toggles 16 GPIOs continuously, configuring them as outputs (GPIO3.1 to GPIO3.16) through sys interface.

Now according to your claim, the GPIOs that are being toggled through sys interface on A9 should not toggle, because they are being continuously toggled and monitored from M4. But I am able to see both running parallelly, though both belong to same GPIO Bank.

I would like to know why am I able to toggle

Request you to let me know if you require anything else.

Regards,

Balaji. V

Re: Sharing a GPIO bank between A9 and M4 in i.MX6SX

igorpadykov — Mon, 26 Sep 2016 10:53:27 GMT

if you did not configured RDC, then both A9 and M4

will be able to access GPIO.

Best regards
igor

Re: Sharing a GPIO bank between A9 and M4 in i.MX6SX

Balaji_ng — Mon, 26 Sep 2016 12:50:37 GMT

Kindly let me know where (is it in U-Boot or M4 App or as a Kernel driver) and how to configure the RDC?

Regards,

Balaji.V

Re: Sharing a GPIO bank between A9 and M4 in i.MX6SX

igorpadykov — Tue, 27 Sep 2016 00:17:30 GMT

seems it can be done in mach-imx6sx.c
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-imx/mach-imx6sx.c?h=imx_4.1.15_1.0.0_ga
RDC programming examples can be found in
FreeRTOS_BSP_i.MX6SX - Windows installer (REV 1.0.0)
https://www.nxp.com/webapp/sps/download/license.jsp?colCode=FREERTOS_MX6SX_1.0.0_WIN&appType=file1&location=null&DOWNLOAD_ID=null

~igor