i.MX ProcessorsのトピックRe: i.MX 6DQ Synchronous Display Interface Timing Characteristics

i.MX 6DQ Synchronous Display Interface Timing Characteristics

sugiyamatoshihi — Tue, 14 Mar 2017 08:31:44 GMT

I have aquestion about Synchronous Display Interface Timing Characteristics in i.MX 6DQ data sheet.

There is a specification of data holdup/setup timing in figure 71 and Table 70.

I think this LCD interface only output clock, data and controll signal to LCD. So, I wonder why there is setup time specification. I suppose usually data delay time and hold time from clock edge are specified for output signal.

I attched a doc.

I checked below, but I couldn't understand clearly.

https://community.nxp.com/message/597894

Best Regards,

Sugiyama

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

art — Tue, 14 Mar 2017 11:46:45 GMT

Actually, there are just some confusing names for the timing parameters. And, you are right, here IP19 can be treated as the Data Delay time and IP18 - as the Data Hold time parameters.

Have a great day,
Artur

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Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

sugiyamatoshihi — Wed, 15 Mar 2017 05:01:49 GMT

Hi, Artur,

Thank you for clarifing it.

Thanks,

Sugiyama

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

sugiyamatoshihi — Wed, 22 Mar 2017 05:45:51 GMT

Hi, Artur,

I wrote a document to understand easier to to understand the DI clock timing.

Could you review the doc. if my understanding is correct?

Best Regards,

Sugiyama

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

art — Wed, 22 Mar 2017 07:41:12 GMT

Yes, your understanding is correct.

Best Regards,

Artur

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

sugiyamatoshihi — Fri, 24 Mar 2017 00:08:20 GMT

Hi, Artur,

Thanks for review and answer.

Best Regards,

Sugiyama

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

t-iishii — Wed, 29 Mar 2017 12:56:29 GMT

Hello Artur,

I'm very confuse about IPP_DISP_CLK porarity in Figure 71 in IMX6DQAEC.

Mr Sugiyama say in attached document, that Figure 71 is missed,

Between local start point and falling edge of IPP_DISP_CLK is Tdicd.

Between local start point and rising edge of IPP_DISP_CLK is Tdicu.

But you say A.2(Answer of Q2) in thread About setup/hold time of synchronous display in i.MX6DQ.

to Figure 71 is correct.

Which is a correct answer?

If it is not clear, we can not discuss about table 70 in IMX6DQAEC,

because it is very ambiguous about IP18, IP19 meening.

My goal is to understand how to define each register value to fit a requirement of each LCD panel.

For it, please express a meaning of each timing parameter like,

IP18 : time from IPP_DATA valid to falling edge of IPP_DISP_CLK if IPP_DISP_CLK is not inverted..

IP19: time from falling edge of IPP_DISP_CLK, if IPP_DISP_CLK is not inverted.

Note: DISP_CLK_DOWN > DISP_CLK_UP.

Best regards,

Ishii.

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

t-iishii — Mon, 03 Apr 2017 13:10:33 GMT

Can anyone comment to me?

Best regard,

Ishii.

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

karina_valencia — Tue, 04 Apr 2017 14:51:37 GMT

art‌ please continue with the follow up

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

art — Thu, 06 Apr 2017 10:16:28 GMT

Dear Takayuki Ishii,

Yes, you are right. In case of IPP_DISP_CLK is not inverted, these timings can be treated as follows.

IP18: IPP_DATA valid to falling edge of IPP_DISP_CLK.

IP19: falling edge of IPP_DISP_CLK to IPP_DATA invalid.

Best Regards,
Artur

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

t-iishii — Thu, 06 Apr 2017 13:54:16 GMT

Hi,

Artur

Thank you for your response.

Which timing does it triggered a data transition?

Local start time is correct?

Best regards,

Ishii.

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

art — Fri, 07 Apr 2017 06:39:10 GMT

Yes, you are right. The local start point triggers the data transfer according to the timings above.

Best Regards,

Artur

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

t-iishii — Thu, 13 Apr 2017 01:31:03 GMT

Hello Artur

Thank you for your comment and sorry for my late reply.

If DISP_CLK_UP = 0x00 and DISP_CLK_DOWN=0x02,

IP18 Tdsu(Min) will larger than Tdus(Typ) value.

We use following register setting

DI_CLK = 108MHz

DISP_CLK_PERIOD = 0x20

DI_CLK _PERIOD = 0x10

DISP_CLK_UP = 0x00

DISP_CLK_DOWN = 0x02

in this time

Tdiclk = 9.26nsec

Tdicd = 1/2(9.26ns * ceil( 2x (0x02/2) / (0x10/16) ) = 9.26

Tdicu = 1/2(9.26ns * ceil( 2x (0x00/2) / (0x10/16) ) = 0

Tdus(Min) = Tdicd - 1.24 = 9.26 - 1.24 = 8.02

Tdsu(Typ) = Tdicu = 0

So Tdus(Min): 8.02 > Tdsu(Typ): 0

In this case, how do we think about it?

Best regards,

Ishii.

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

t-iishii — Fri, 14 Apr 2017 13:51:25 GMT

Hi,

Artur

Possibly does "Tdsu" mean a time from local start point to data valid?

" _______ ___|___ _______ ___"

"IPP_DISP_CLK_N| |_______| | |_______| |_______| "

" Tdicu |<->|"

" ________________________| |_______________ ___________"

" Tdsu(Typ)________________________XXXXX_______________X___________"

" Tdicd-1.24 |<-------->||<- 1.24"

" ________________________| |_______________ ____"

" Tdsu(min)_________________________XXXXXXXXXXX_______________X____"

" | <-- local start point"

Normally, data setup mean from data valid to edge for data latch.

" ___________ __________"

" data enable |_________________|"

" Tdsu |<------>|"

" ____________ |________|__ _______"

" DATA ____________XXXXXXXX____________X_______"

Best regards,

Ishii.

Re: i.MX 6DQ Synchronous Display Interface Timing Characteristics

t-iishii — Mon, 17 Apr 2017 13:38:14 GMT

Hi Artur,

Thank you for your kindly support.

But I can not explain this logic to my customer yet.

Following are register value by Linux BSP 4.1.15 + i.MX6QSabre-SDP

IPU2_PM :0x02A000E0 = 0x08100810 -> 0b00-00 1000 0-001 0000 : 00-00 1000 0-001 0000
** DI1_CLK_PERIOD_1[29:23] = 0b0010000 = 0x10
** DI1_CLK_PERIOD_0[22:16] = 0b0010000 = 0x10
** DI0_CLK_PERIOD_1[13:7] = 0b0010000 = 0x10
** DI0_CLK_PERIOD_0[6:0] = 0b0010000 = 0x10
IPU2_DI0_BS_CLKGEN0:0x02A40004 = 0
** DI0_DISP_CLK_OFFSET[24:16]
** DI0_DISP_CLK_PERIOD[11:0]
IPU2_DI0_BS_CLKGEN1:0x02A40008 = 0
** DISP_CLK_DOWN[24:16]
** DISP_CLK_UP[8:0]
IPU2_DI1_BS_CLKGEN0:0x02A48004 = 0x00000010
** DI1_DISP_CLK_OFFSET[24:16] = 0000
** DI1_DISP_CLK_PERIOD[11:0] = 0010
IPU2_DI1_BS_CLKGEN1:0x02A48008 = 0x00010000
** DISP_CLK_DOWN[24:16] = 01
** DISP_CLK_UP[8:0] = 00

Please inform me, how design IPU timing to fit LCD panel specification.

Best regards,

Ishii.