<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: SAI transmit FIFO pointers</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/647772#M98963</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Linas&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please refer to sect.42.3.2.2 FIFO reset&amp;nbsp; i.MX6UL and description&lt;/P&gt;&lt;P&gt;of register RMI2Sx_TCSR[FR] FIFO Reset.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf" title="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 27 Apr 2017 23:11:20 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-04-27T23:11:20Z</dc:date>
    <item>
      <title>SAI transmit FIFO pointers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/647771#M98962</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am handling SAI audio interface on imx6. There is a SAI Transmit FIFO reg (TFR) with WFP and RFP pointers for transmit data channel. At what condition WFP and RFP pointers are reset to 0?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the reference manual WFP is incremented after each valid write to TDR. Does the WFP is incremented until max value 2^6?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Br,&lt;/P&gt;&lt;P&gt;Linas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Apr 2017 13:13:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/647771#M98962</guid>
      <dc:creator>linasstaisiunas</dc:creator>
      <dc:date>2017-04-27T13:13:10Z</dc:date>
    </item>
    <item>
      <title>Re: SAI transmit FIFO pointers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/647772#M98963</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Linas&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please refer to sect.42.3.2.2 FIFO reset&amp;nbsp; i.MX6UL and description&lt;/P&gt;&lt;P&gt;of register RMI2Sx_TCSR[FR] FIFO Reset.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf" title="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Apr 2017 23:11:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/647772#M98963</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-04-27T23:11:20Z</dc:date>
    </item>
    <item>
      <title>Re: SAI transmit FIFO pointers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/647773#M98964</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I understand what is written in the sect.42.3.2.2. But I am interested in I2Sx_TFRn and I2Sx_RFRn registers which store read/write pointers. Is it possible to calculate fill level of transmit and receive buffers using these pointer values?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 May 2017 12:52:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/647773#M98964</guid>
      <dc:creator>linasstaisiunas</dc:creator>
      <dc:date>2017-05-02T12:52:02Z</dc:date>
    </item>
    <item>
      <title>Re: SAI transmit FIFO pointers</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/647774#M98965</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;please refer to sect.42.3.5.2 FIFO pointers&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;Is it possible to calculate fill level of transmit and receive buffers using these pointer values?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am afraid no&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 May 2017 23:40:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SAI-transmit-FIFO-pointers/m-p/647774#M98965</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-05-02T23:40:31Z</dc:date>
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  </channel>
</rss>

