<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic imx6 remapping uart question in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6-remapping-uart-question/m-p/647161#M98860</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am remapping the uart1 and uart5 but there are a hex number after the pin name, I could not find what it is for:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;iomuxc {&lt;BR /&gt; imx6qdl-scm {&lt;BR /&gt; /* add MUXing entry for SD2 4-bit interface and configure control pins */&lt;BR /&gt; pinctrl_uart2_my: uart2grp {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; MX6QDL_PAD_EIM_D26__UART2_TX_DATA &lt;STRONG&gt;0x1f0b1&lt;/STRONG&gt;&lt;BR /&gt; MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1f0b1&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;/*remapping uart1 for GPS*/&lt;BR /&gt; pinctrl_uart1_my: uart1grp {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA &lt;STRONG&gt;0x1b0b1&lt;/STRONG&gt;&lt;BR /&gt; MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;};&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;what is it? 0x1f0b1 &amp;nbsp;0x1b0b1&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Colud you advice?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 25 Jan 2017 21:54:58 GMT</pubDate>
    <dc:creator>aaronpadilla</dc:creator>
    <dc:date>2017-01-25T21:54:58Z</dc:date>
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      <title>imx6 remapping uart question</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6-remapping-uart-question/m-p/647161#M98860</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am remapping the uart1 and uart5 but there are a hex number after the pin name, I could not find what it is for:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;amp;iomuxc {&lt;BR /&gt; imx6qdl-scm {&lt;BR /&gt; /* add MUXing entry for SD2 4-bit interface and configure control pins */&lt;BR /&gt; pinctrl_uart2_my: uart2grp {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; MX6QDL_PAD_EIM_D26__UART2_TX_DATA &lt;STRONG&gt;0x1f0b1&lt;/STRONG&gt;&lt;BR /&gt; MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1f0b1&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;/*remapping uart1 for GPS*/&lt;BR /&gt; pinctrl_uart1_my: uart1grp {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA &lt;STRONG&gt;0x1b0b1&lt;/STRONG&gt;&lt;BR /&gt; MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;};&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;what is it? 0x1f0b1 &amp;nbsp;0x1b0b1&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Colud you advice?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jan 2017 21:54:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6-remapping-uart-question/m-p/647161#M98860</guid>
      <dc:creator>aaronpadilla</dc:creator>
      <dc:date>2017-01-25T21:54:58Z</dc:date>
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    <item>
      <title>Re: imx6 remapping uart question</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6-remapping-uart-question/m-p/647162#M98861</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Aaron,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the IOMUX chapter of reference Manual you can find followng registers:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26&lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The number you are asking for is the value of register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 while the name of the mcro is related to MUX function which is associated to&amp;nbsp;IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Carlos&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Jan 2017 22:40:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6-remapping-uart-question/m-p/647162#M98861</guid>
      <dc:creator>Carlos_Musich</dc:creator>
      <dc:date>2017-01-26T22:40:45Z</dc:date>
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  </channel>
</rss>

