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    <title>topic Re: imx6slevk ldo in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6slevk-ldo/m-p/644334#M98330</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Q. i dont know why INT's pin connect REF_CLK_24M.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A. Actually, REF_CLK_24M is the regular multipurpose I/O pin, as most of other processor's pins, whose function is controlled by the IOMUX module. Here, the REF_CLK_24M pin is just used as the interrupt-enabled GPIO input.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Q. VDD_ARM_IN1 value and VDD_ARM_CAP value have what differences?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A. It depends on which mode the built-in Power Management Unit (PMU) module operates in. In LDO bypas mode, VDD_ARM_IN is equal to VDD_ARM_CAP. In case of LDO enabled mode, it depends on the value of VDD_ARM_IN and the LDO regulation setpoint, selected in the PMU_REG_CORE registed in software. The default setpoint value is 1.1V. Note that, for normal regulation, the LDO input voltage (VDD_ARM_IN) should be at least 150mV higher than the output setpoint.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 29 Sep 2016 10:12:11 GMT</pubDate>
    <dc:creator>art</dc:creator>
    <dc:date>2016-09-29T10:12:11Z</dc:date>
    <item>
      <title>imx6slevk ldo</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6slevk-ldo/m-p/644333#M98329</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;i use MCIMX6SLEVK,i have a problem at MMPF0100F1EP,schematic diagram as follow&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/5528iE2BC77FE2D944751/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&amp;nbsp; i dont know why INT's pin connect &amp;nbsp;REF_CLK_24M.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/5589i24C033F06BDE17C9/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;VDD_ARM_IN1 value and VDD_ARM_CAP value &amp;nbsp;have what differences?&amp;nbsp;Whether ldo must be have.&lt;/P&gt;&lt;P&gt;who can give me some advices ?&lt;/P&gt;&lt;P&gt;THANKS&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 23 Sep 2016 02:37:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6slevk-ldo/m-p/644333#M98329</guid>
      <dc:creator>威杨</dc:creator>
      <dc:date>2016-09-23T02:37:11Z</dc:date>
    </item>
    <item>
      <title>Re: imx6slevk ldo</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6slevk-ldo/m-p/644334#M98330</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Q. i dont know why INT's pin connect REF_CLK_24M.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A. Actually, REF_CLK_24M is the regular multipurpose I/O pin, as most of other processor's pins, whose function is controlled by the IOMUX module. Here, the REF_CLK_24M pin is just used as the interrupt-enabled GPIO input.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Q. VDD_ARM_IN1 value and VDD_ARM_CAP value have what differences?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A. It depends on which mode the built-in Power Management Unit (PMU) module operates in. In LDO bypas mode, VDD_ARM_IN is equal to VDD_ARM_CAP. In case of LDO enabled mode, it depends on the value of VDD_ARM_IN and the LDO regulation setpoint, selected in the PMU_REG_CORE registed in software. The default setpoint value is 1.1V. Note that, for normal regulation, the LDO input voltage (VDD_ARM_IN) should be at least 150mV higher than the output setpoint.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Sep 2016 10:12:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6slevk-ldo/m-p/644334#M98330</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2016-09-29T10:12:11Z</dc:date>
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