i.MX ProcessorsのトピックMemory Timing issue on custom board based on i.MX28

Memory Timing issue on custom board based on i.MX28

Rt1z — Tue, 29 Nov 2011 00:15:10 GMT

Hi All,

We have build a custom board with i.mx280 and ddr2 from micron 64mb.Looks like its memory timing issue, we are using default bootlet setting , with obvious change , bank size to 4 banks and SDRAM_SIZE .

Issue we see : when writer to DDR2 ( DDR base to max size), its fails after some writer ( random ) , so if we add delay write and read and then write , work well.

So , this looks like memory timing issue.

Will appreciate any one have experience dealing this issue , point me in right direction !!!!

Any help appreciated !!!

Thanks ,

Re: Memory Timing issue on custom board based on i.MX28

AhmetYUCE — Tue, 29 Nov 2011 07:57:40 GMT

If i understand correctly you receive error messages from bootlet? If you have iMX28 EVK try running your modified bootlet on it. Although it have 8 bank memory, there shouldn't be any problem 4 bank settings. If your modified SW O.K. then do a electrical verification on DDR lines with a proper scope and active probes. Both for timing and voltage levels. There could be an issue with PCB routing, stackup or decoupling. Regards Ahmet

Re: Memory Timing issue on custom board based on i.MX28

Rt1z — Wed, 30 Nov 2011 18:54:14 GMT

Thanks Ahmet for reply,

I did memory testing from bootlet and also from the kernel, (after linux_prep jumps to the kernel to uncompressed misc.c)

from the boot_prep i am trying to writer all DRAM ( 64 Mbyte ) 4bytes @ a time. which fails randomly. Its pass if we adding delay (by reading back ) after each write.

same thing from the test code in the misc.c ( made sure we are writing in free mem space).

Same boot image work on my EVA board .

Any input on thing in s/w ( bootlet ) i need to change ( apart for the bank change DRAM[31] and SDRAM_SIZE) ? any help appreciated.

BR,