topic Concurrent DDR writes from SDMA and AP Core in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/Concurrent-DDR-writes-from-SDMA-and-AP-Core/m-p/643477#M98244 <HTML><HEAD></HEAD><BODY><P>Hi</P><P></P><P>how are concurrent writes from SDMA FU Bursts and writes from A9 Core to non-cached memory &nbsp;are arbitrated? Is it possible to give SDMA writes prio over A9 Core writes?</P><P></P><P>Thanks</P><P>Rolf</P></BODY></HTML> Mon, 26 Dec 2016 11:20:58 GMT rolfw 2016-12-26T11:20:58Z Concurrent DDR writes from SDMA and AP Core https://community.nxp.com/t5/i-MX-Processors/Concurrent-DDR-writes-from-SDMA-and-AP-Core/m-p/643477#M98244 <HTML><HEAD></HEAD><BODY><P>Hi</P><P></P><P>how are concurrent writes from SDMA FU Bursts and writes from A9 Core to non-cached memory &nbsp;are arbitrated? Is it possible to give SDMA writes prio over A9 Core writes?</P><P></P><P>Thanks</P><P>Rolf</P></BODY></HTML> Mon, 26 Dec 2016 11:20:58 GMT https://community.nxp.com/t5/i-MX-Processors/Concurrent-DDR-writes-from-SDMA-and-AP-Core/m-p/643477#M98244 rolfw 2016-12-26T11:20:58Z Re: Concurrent DDR writes from SDMA and AP Core https://community.nxp.com/t5/i-MX-Processors/Concurrent-DDR-writes-from-SDMA-and-AP-Core/m-p/643478#M98245 <HTML><HEAD></HEAD><BODY><P>Hi Rolf</P><P></P><P>arbitration is handled by nic-301 (its documentation can be found on arm.com)</P><P>please check Chapter 45 Network Interconnect Bus System (NIC-301) i.MX6DQ Reference Manual </P><P><A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fcache.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fref_manual%2FIMX6DQRM.pdf" rel="nofollow" target="_blank">http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf</A></P><P></P><P>Best regards<BR />igor<BR />-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Mon, 26 Dec 2016 23:27:09 GMT https://community.nxp.com/t5/i-MX-Processors/Concurrent-DDR-writes-from-SDMA-and-AP-Core/m-p/643478#M98245 igorpadykov 2016-12-26T23:27:09Z Re: Concurrent DDR writes from SDMA and AP Core https://community.nxp.com/t5/i-MX-Processors/Concurrent-DDR-writes-from-SDMA-and-AP-Core/m-p/643479#M98246 <HTML><HEAD></HEAD><BODY><P>Perfect!&nbsp;</P><P></P><P>Great thanks!</P><P>Rolf</P></BODY></HTML> Tue, 27 Dec 2016 08:44:30 GMT https://community.nxp.com/t5/i-MX-Processors/Concurrent-DDR-writes-from-SDMA-and-AP-Core/m-p/643479#M98246 rolfw 2016-12-27T08:44:30Z