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    <title>i.MX ProcessorsのトピックPCIe EP DMA write to i.MX6 RAM</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-EP-DMA-write-to-i-MX6-RAM/m-p/643239#M98202</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Under the following conditions:&lt;/P&gt;&lt;P&gt;-. i.MX6 configured as PCIe RC&lt;/P&gt;&lt;P&gt;- The i.MX6 is connected to PCIe EP&lt;/P&gt;&lt;P&gt;- The EP wants to perform DMA write operation to the I.MX6 RAM&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does this scenario supported?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Eyal&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 03 Apr 2017 14:22:36 GMT</pubDate>
    <dc:creator>egabay1</dc:creator>
    <dc:date>2017-04-03T14:22:36Z</dc:date>
    <item>
      <title>PCIe EP DMA write to i.MX6 RAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-EP-DMA-write-to-i-MX6-RAM/m-p/643239#M98202</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Under the following conditions:&lt;/P&gt;&lt;P&gt;-. i.MX6 configured as PCIe RC&lt;/P&gt;&lt;P&gt;- The i.MX6 is connected to PCIe EP&lt;/P&gt;&lt;P&gt;- The EP wants to perform DMA write operation to the I.MX6 RAM&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does this scenario supported?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Eyal&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Apr 2017 14:22:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-EP-DMA-write-to-i-MX6-RAM/m-p/643239#M98202</guid>
      <dc:creator>egabay1</dc:creator>
      <dc:date>2017-04-03T14:22:36Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe EP DMA write to i.MX6 RAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-EP-DMA-write-to-i-MX6-RAM/m-p/643240#M98203</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Eyal,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In EP's system, EP can access the reserved ddr memory&amp;nbsp;&amp;nbsp;&amp;nbsp; (default address:0x40000000) of PCIe RC's system, by the&amp;nbsp;&amp;nbsp; interconnection between PCIe EP and PCIe RC. So I don´t see a problem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here is a link of a validation&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-95014"&gt;i.MX6Q PCIe EP/RC Validation System&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Jaime&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Apr 2017 14:53:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-EP-DMA-write-to-i-MX6-RAM/m-p/643240#M98203</guid>
      <dc:creator>jamesbone</dc:creator>
      <dc:date>2017-04-04T14:53:06Z</dc:date>
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