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    <title>topic About DDR addr routing problem in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-DDR-addr-routing-problem/m-p/642553#M98090</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;I find the fact that the length of DDR addr routing is more than 2000mil in SABRESDB_DESIGNFILES. And the clock is only about 2000mil.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; But the addr length should be no more than clock length as described by designed guide and checklist.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; So, Why does the&amp;nbsp;SABRESDB_DESIGNFILES can not be confirmed with the design guide?&lt;/P&gt;&lt;P&gt;B.R.&lt;/P&gt;&lt;P&gt;Nelson.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 12 Mar 2017 03:47:52 GMT</pubDate>
    <dc:creator>nelsonli</dc:creator>
    <dc:date>2017-03-12T03:47:52Z</dc:date>
    <item>
      <title>About DDR addr routing problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-DDR-addr-routing-problem/m-p/642553#M98090</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;I find the fact that the length of DDR addr routing is more than 2000mil in SABRESDB_DESIGNFILES. And the clock is only about 2000mil.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; But the addr length should be no more than clock length as described by designed guide and checklist.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; So, Why does the&amp;nbsp;SABRESDB_DESIGNFILES can not be confirmed with the design guide?&lt;/P&gt;&lt;P&gt;B.R.&lt;/P&gt;&lt;P&gt;Nelson.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 12 Mar 2017 03:47:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-DDR-addr-routing-problem/m-p/642553#M98090</guid>
      <dc:creator>nelsonli</dc:creator>
      <dc:date>2017-03-12T03:47:52Z</dc:date>
    </item>
    <item>
      <title>Re: About DDR addr routing problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-DDR-addr-routing-problem/m-p/642554#M98091</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Nelson&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;design guide was developed and validated later than Sabre reference board&lt;/P&gt;&lt;P&gt;was designed and recommended to follow official design guide and checklist.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 12 Mar 2017 23:03:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-DDR-addr-routing-problem/m-p/642554#M98091</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-03-12T23:03:51Z</dc:date>
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