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    <title>topic About i.MX7Dual DDR Routing Rules in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-i-MX7Dual-DDR-Routing-Rules/m-p/642096#M98006</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Due to i.MX7 layout review check list isn’t released, we provide i.MX6 check list for customer now.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But some layout rules are conflict between i.MX6 and i.MX7.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;For example, i.MX6 check list-DRAM bus length check.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It says” the maximum length difference should be less than 25 mils”.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But at i.MX6 Hardware development guide, it shows +/-25mils is acceptable.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;So the rule in i.MX6 check list seems to be more strictly.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Our question is we read i.MX7 Hardware development guide.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The rule it shows is +/- 55 mils.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is it the right value for i.MX7 DDR trace length check?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Or we should follow i.MX6 check list to do this layout of DDR circuit.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="i.mx6ddr_routing.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/13590i64DD82C9CD2E3D94/image-size/large?v=v2&amp;amp;px=999" role="button" title="i.mx6ddr_routing.png" alt="i.mx6ddr_routing.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="i.mx7ddr_routing.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/13630iA74F3C9FB1AEF794/image-size/large?v=v2&amp;amp;px=999" role="button" title="i.mx7ddr_routing.png" alt="i.mx7ddr_routing.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 24 Jan 2017 09:54:43 GMT</pubDate>
    <dc:creator>felixhsu</dc:creator>
    <dc:date>2017-01-24T09:54:43Z</dc:date>
    <item>
      <title>About i.MX7Dual DDR Routing Rules</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-i-MX7Dual-DDR-Routing-Rules/m-p/642096#M98006</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Due to i.MX7 layout review check list isn’t released, we provide i.MX6 check list for customer now.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But some layout rules are conflict between i.MX6 and i.MX7.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;For example, i.MX6 check list-DRAM bus length check.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It says” the maximum length difference should be less than 25 mils”.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But at i.MX6 Hardware development guide, it shows +/-25mils is acceptable.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;So the rule in i.MX6 check list seems to be more strictly.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Our question is we read i.MX7 Hardware development guide.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The rule it shows is +/- 55 mils.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is it the right value for i.MX7 DDR trace length check?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Or we should follow i.MX6 check list to do this layout of DDR circuit.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="i.mx6ddr_routing.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/13590i64DD82C9CD2E3D94/image-size/large?v=v2&amp;amp;px=999" role="button" title="i.mx6ddr_routing.png" alt="i.mx6ddr_routing.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="i.mx7ddr_routing.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/13630iA74F3C9FB1AEF794/image-size/large?v=v2&amp;amp;px=999" role="button" title="i.mx7ddr_routing.png" alt="i.mx7ddr_routing.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Jan 2017 09:54:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-i-MX7Dual-DDR-Routing-Rules/m-p/642096#M98006</guid>
      <dc:creator>felixhsu</dc:creator>
      <dc:date>2017-01-24T09:54:43Z</dc:date>
    </item>
    <item>
      <title>Re: About i.MX7Dual DDR Routing Rules</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-i-MX7Dual-DDR-Routing-Rules/m-p/642097#M98007</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; i.MX7 DDRC is not the same as i.MX6 MMDC, therefore please use the&amp;nbsp;Hardware&lt;/P&gt;&lt;P&gt;Development Guide for i.MX7.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jan 2017 04:36:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-i-MX7Dual-DDR-Routing-Rules/m-p/642097#M98007</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-01-25T04:36:39Z</dc:date>
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