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    <title>topic Re: DRAM Calibration using DDR Stress Test Tool V2.60  in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-Calibration-using-DDR-Stress-Test-Tool-V2-60/m-p/639707#M97547</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Please create request&amp;nbsp;&lt;A class="link-titled" href="http://www.nxp.com/support/sales-and-support:SUPPORTHOME" title="http://www.nxp.com/support/sales-and-support:SUPPORTHOME"&gt;Sales and Support|NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;and send DDR schematic (connections between i.MX6 and &lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;MT41K1G16&lt;/SPAN&gt;).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 21 Mar 2017 04:29:17 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2017-03-21T04:29:17Z</dc:date>
    <item>
      <title>DRAM Calibration using DDR Stress Test Tool V2.60</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-Calibration-using-DDR-Stress-Test-Tool-V2-60/m-p/639704#M97544</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am working DDR calibration using NXP DDR Test tool. We have imx6qp based custom hardware.&lt;/P&gt;&lt;P&gt;I am following the below procedure&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. Run NXP DDR test tool to get the calibrated values for the MMDC registers (12 registers)&lt;/P&gt;&lt;P&gt;2. Run the Calibration test multiple times and capture the results.&lt;/P&gt;&lt;P&gt;3. Based on the values in the multiple iterations, take the values which are mostly repeated&lt;/P&gt;&lt;P&gt;4. Update the script with the selected values&lt;/P&gt;&lt;P&gt;5. Run the DDR test tool, load the updated script and execute the stress test instead of calibration test&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Most of the times the stress test fails and very few time it succeeds.&lt;/P&gt;&lt;P&gt;The overnight test fails all the times.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I would like to know what is the best way to get the calibrated values.&lt;/P&gt;&lt;P&gt;If it is difficult to get optimised values for a single board, is it possible to get the optimisedregister values which run across the boards.&lt;/P&gt;&lt;P&gt;Appreciate any useful information that will help me to completed this process.&lt;/P&gt;&lt;P&gt;Below capture logs in fail and pass cases.&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Kishor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Failure case:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;DDR Stress Test Iteration 1&lt;BR /&gt;Current Temperature: 40&lt;BR /&gt;============================================&lt;/P&gt;&lt;P&gt;DDR Freq: 528 MHz&lt;BR /&gt;t0.1: data is addr test&lt;BR /&gt;t0: memcpy10 SSN x64 test&lt;BR /&gt;t1: memcpy8 SSN x64 test&lt;BR /&gt;t2: byte-wise SSN x64 test&lt;BR /&gt;t3: memcpy11 random pattern test&lt;BR /&gt;test1 Address: 0x18695440&lt;BR /&gt;Data initally read was: 0x55555555&lt;BR /&gt;Data re-read is: 0x55555555&lt;BR /&gt;But pattern was: 0x5e5f95f8&lt;BR /&gt;Bit location: 0x0b0ac0ad&lt;BR /&gt;&lt;SPAN style="color: #ff0000;"&gt;Error: failed to run stress test!!!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Success case:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DDR Stress Test Iteration 1&lt;BR /&gt;Current Temperature: 42&lt;BR /&gt;============================================&lt;/P&gt;&lt;P&gt;DDR Freq: 528 MHz&lt;BR /&gt;t0.1: data is addr test&lt;BR /&gt;t0: memcpy10 SSN x64 test&lt;BR /&gt;t1: memcpy8 SSN x64 test&lt;BR /&gt;t2: byte-wise SSN x64 test&lt;BR /&gt;t3: memcpy11 random pattern test&lt;BR /&gt;t4: IRAM_to_DDRv2 test&lt;BR /&gt;t5: IRAM_to_DDRv1 test&lt;BR /&gt;t6: read noise walking ones and zeros test&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #008000;"&gt;Success: DDR Stress test completed!!!&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 09 Mar 2017 20:30:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DRAM-Calibration-using-DDR-Stress-Test-Tool-V2-60/m-p/639704#M97544</guid>
      <dc:creator>kishorr</dc:creator>
      <dc:date>2017-03-09T20:30:13Z</dc:date>
    </item>
    <item>
      <title>Re: DRAM Calibration using DDR Stress Test Tool V2.60</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-Calibration-using-DDR-Stress-Test-Tool-V2-60/m-p/639705#M97545</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Perhaps the problem relates to some inaccuracy&amp;nbsp; in memory PCB design.&lt;/P&gt;&lt;P&gt;You may look at sections 3.3.1 (Identifying Issue on Calibrations) and &lt;BR /&gt;3.3.2 (Identifying Issue on Stress Test) of the following document.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-101708"&gt;Freescale i.MX6 DRAM Port Application Guide-DDR3&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please check Your PCB design&amp;nbsp; using Chapter 3 (i.MX 6 Series Layout Recommendations) &lt;BR /&gt;of the&amp;nbsp; Hardware Development Guide&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://cache.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf" title="http://cache.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf"&gt;http://cache.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; In particular, please use Excel page named “MX6 DRAM Bus Length Check” in “HW Design&lt;/P&gt;&lt;P&gt;Checking List&amp;nbsp; for i.Mx6”, linked below.&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;A href="https://community.nxp.com/docs/DOC-93819"&gt;https://community.nxp.com/docs/DOC-93819&lt;/A&gt;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&amp;nbsp; Also, You may&amp;nbsp; verify Your design, using the recent design checklist, that may be found&lt;/P&gt;&lt;P&gt;in the HW_Design_Checking_List&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 10 Mar 2017 04:15:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DRAM-Calibration-using-DDR-Stress-Test-Tool-V2-60/m-p/639705#M97545</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-03-10T04:15:15Z</dc:date>
    </item>
    <item>
      <title>Re: DRAM Calibration using DDR Stress Test Tool V2.60</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-Calibration-using-DDR-Stress-Test-Tool-V2-60/m-p/639706#M97546</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you very much Yuri. The&amp;nbsp;PCB design looks to be as per the recommendations.&lt;/P&gt;&lt;P&gt;Also on our current hardware, we are using the part &amp;nbsp;MT41K1G16 (2Gbyte)&amp;nbsp;&lt;/P&gt;&lt;P&gt;Total 4 parts are used which should provide 8Gbytes of memory, but as CS0 is only used total accessible memory is 4Gbytes. CS1 not connected.&lt;/P&gt;&lt;P&gt;I have attached NXP excel sheet that we using to create the DDR script file.&amp;nbsp;I was thinking if anything is wrong with the configuration provided in the excel sheet. I am attaching it. In case you find any issues please let me know.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE width="430"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD colspan="2" style="border-right: 1.0pt solid black;" width="430"&gt;Device Information&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Manufacturer:&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;Micron&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Memory part number:&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;MT41K1G16&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Memory type:&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;DDR3-1600&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;DRAM density (Gb)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;8&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;DRAM Bus Width&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;16&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Number of Banks&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;8&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Number of ROW Addresses&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;16&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Number of COLUMN Addresses&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;10&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Page Size (K)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;2&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Self-Refresh Temperature (SRT)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;Normal&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;tRCD=tRP=CL (ns)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;21&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;tRC Min (ns)&lt;/TD&gt;&lt;TD style="border-left: none;"&gt;21&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;tRAS Min (ns)&lt;/TD&gt;&lt;TD style="border-left: none;"&gt;62.5&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD colspan="2" style="border-right: 1.0pt solid black;"&gt;System Information&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;i.Mx Part&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;i.Mx6Q&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Bus Width&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;64&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;" width="285"&gt;Density per chip select (Gb)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;32&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Number of Chip Selects used&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;1&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;" width="285"&gt;Total DRAM Density (Gb)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;32&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;DRAM Clock Freq (MHz)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;528&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;DRAM Clock Cycle Time (ns)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;1.894&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;Address Mirror (for CS1)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;Disable&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD colspan="2" style="border-right: 1.0pt solid black;"&gt;SI Configuration&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;DRAM DSE Setting - DQ/DQM (ohm)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;40&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;"&gt;DRAM DSE Setting - ADDR/CMD/CTL (ohm)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;40&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;" width="285"&gt;DRAM DSE Setting - CK (ohm)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;40&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;" width="285"&gt;DRAM DSE Setting - DQS (ohm)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;40&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border-top: none;" width="285"&gt;System ODT Setting (ohm)&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none;"&gt;60&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Kishor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Mar 2017 21:37:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DRAM-Calibration-using-DDR-Stress-Test-Tool-V2-60/m-p/639706#M97546</guid>
      <dc:creator>kishorr</dc:creator>
      <dc:date>2017-03-15T21:37:07Z</dc:date>
    </item>
    <item>
      <title>Re: DRAM Calibration using DDR Stress Test Tool V2.60</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-Calibration-using-DDR-Stress-Test-Tool-V2-60/m-p/639707#M97547</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Please create request&amp;nbsp;&lt;A class="link-titled" href="http://www.nxp.com/support/sales-and-support:SUPPORTHOME" title="http://www.nxp.com/support/sales-and-support:SUPPORTHOME"&gt;Sales and Support|NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;and send DDR schematic (connections between i.MX6 and &lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;MT41K1G16&lt;/SPAN&gt;).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Mar 2017 04:29:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DRAM-Calibration-using-DDR-Stress-Test-Tool-V2-60/m-p/639707#M97547</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-03-21T04:29:17Z</dc:date>
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