topic Re: difference in AUD5_RXD pin mux in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/difference-in-AUD5-RXD-pin-mux/m-p/639564#M97514 <HTML><HEAD></HEAD><BODY><P>Hi Mohsen</P><P></P><P>recommended to use Table 4-1. Pin Assignments and sect.35.5.43 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1) description, it is more accurate,</P><P>while Table17-1 gives generic AUDMUX module description.</P><P></P><P>Best regards<BR />igor<BR />-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Wed, 25 Jan 2017 09:50:12 GMT igorpadykov 2017-01-25T09:50:12Z difference in AUD5_RXD pin mux https://community.nxp.com/t5/i-MX-Processors/difference-in-AUD5-RXD-pin-mux/m-p/639563#M97513 <HTML><HEAD></HEAD><BODY><P>Hello Dears</P><P>In Table4-1 in IMX6SXRM Noted AUD5_RXD is ALT4 of KEY_ROW1.</P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/12701iB90C57DBE2519834/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /></span></P><P><SPAN class="" lang="en"><SPAN>However</SPAN></SPAN> Table17-1 <SPAN class="" lang="en"> <SPAN class="">does not show</SPAN></SPAN></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/12661iB9E2AB6D9A097C96/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /></span></P><P>Can everyone <SPAN class="" lang="en"><SPAN>explain</SPAN> <SPAN>this</SPAN> <SPAN class="">difference</SPAN></SPAN>.</P><P>best regards.</P></BODY></HTML> Wed, 25 Jan 2017 05:25:45 GMT https://community.nxp.com/t5/i-MX-Processors/difference-in-AUD5-RXD-pin-mux/m-p/639563#M97513 mohsengh 2017-01-25T05:25:45Z Re: difference in AUD5_RXD pin mux https://community.nxp.com/t5/i-MX-Processors/difference-in-AUD5-RXD-pin-mux/m-p/639564#M97514 <HTML><HEAD></HEAD><BODY><P>Hi Mohsen</P><P></P><P>recommended to use Table 4-1. Pin Assignments and sect.35.5.43 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1) description, it is more accurate,</P><P>while Table17-1 gives generic AUDMUX module description.</P><P></P><P>Best regards<BR />igor<BR />-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Wed, 25 Jan 2017 09:50:12 GMT https://community.nxp.com/t5/i-MX-Processors/difference-in-AUD5-RXD-pin-mux/m-p/639564#M97514 igorpadykov 2017-01-25T09:50:12Z Re: difference in AUD5_RXD pin mux https://community.nxp.com/t5/i-MX-Processors/difference-in-AUD5-RXD-pin-mux/m-p/639565#M97515 <HTML><HEAD></HEAD><BODY><P>ِDear igor</P><P><SPAN class="" lang="en"><SPAN>Thank you for</SPAN> <SPAN class="">your attention</SPAN></SPAN></P></BODY></HTML> Wed, 25 Jan 2017 10:35:59 GMT https://community.nxp.com/t5/i-MX-Processors/difference-in-AUD5-RXD-pin-mux/m-p/639565#M97515 mohsengh 2017-01-25T10:35:59Z