topic Re: How do I set the ENET_REF_CLK rate in i.MX Processors

How do I set the ENET_REF_CLK rate

michaelworster — Fri, 14 Oct 2016 14:37:34 GMT

I have a design which uses an i.MX6DL processor, my base design makes use of the Ethernet in RMII mode and uses the GPIO_16 to provide the ENET_REF_CLK. Here is the setup from my device tree:

&fec {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_enet>;
   phy-mode = "rmii";
   phy-reset-gpios = <&gpio5 14 0>;
   fsl,magic-packet;
   status = "okay";
};

What I'm seeing is the Ethernet clock is running at 125MHz and I need it running at 50MHz, I was assuming there would be a max-frequency option in the device tree, but I couldn't find any such entry in the fsl-fec.txt file.

Is there a way to limit the clock rate in the device tree?

If not, how should this be handled?

Re: How do I set the ENET_REF_CLK rate

igorpadykov — Fri, 14 Oct 2016 23:35:03 GMT

Hi Michael

device tree entries are parsed in linux/drivers/net/ethernet/freescale/fec_main.c

(function of_property_read_u32()), please also check attached Linux Manual

Chapter 43 Fast Ethernet Controller (FEC) Driver. Seems RMII mode is defined

in uboot, for example one can look at include/configs/mx6slevk.h

#define CONFIG_FEC_XCV_TYPE RMII

and board file in /board/freescale/mx6sxsabresd/mx6sxsabresd.c

setup_fec(). Reference clock produced by CCM_ANALOG_PLL_ENETn.

Best regards
igor
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Re: How do I set the ENET_REF_CLK rate

michaelworster — Sat, 15 Oct 2016 00:36:35 GMT

Thanks for your notes Igor. I've been through fec_main.c and I noticed only the following properties:

num-tx-queues

num-rx-queues

stop-mode

wakeup_irq

phy-reset-duration

So I take it by that, you're saying there is no Device Tree property which can be used to set the clock rate?

Our Ethernet is setup correctly in u-boot, that is we read the ENET_REF_CLK at 50MHz there, but once the kernel initializes it jumps to 125MHz, which is why I was looking in the kernel for notes on how this is selected.

I also did find the information about the CCM_ANALOG_PLL_ENETn register, but I couldn't find in the code where this was done.

I thought perhaps it had to do with the clk_enet_ref_table from arch/arm/mach-imx/clk-imx6q.c

static struct clk_div_table clk_enet_ref_table[] = {
   { .val = 0, .div = 20, },
   { .val = 1, .div = 10, },
   { .val = 2, .div = 5, },
   { .val = 3, .div = 4, },
   { /* sentinel */ }
};

But making adjustments here seemed to have no effect. Do you have another suggestion where I might look for the setting of this register?

Re: How do I set the ENET_REF_CLK rate

igorpadykov — Sat, 15 Oct 2016 00:55:37 GMT

seems this could be done with PHY_INTERFACE_MODE_RMII as in mach-imx6ul.c

linux-2.6-imx.git - Freescale i.MX Linux Tree

Re: How do I set the ENET_REF_CLK rate

michaelworster — Sat, 15 Oct 2016 18:26:12 GMT

Based on feedback from Igor it sounds like there's no way, currently, in the code base/device tree to adjust the ENET_REF clock. As such I've developed a patch file (attached) which checks the device tree and, based on phy-mode, will update the clock rate.