i.MX ProcessorsのトピックRe: IMX6 PCIe Root Complex BAR

IMX6 PCIe Root Complex BAR

GregT — Sat, 21 Jan 2017 17:44:00 GMT

Does anyone know why the iMX6 root complex creates a 64-bit BAR of 1MB? I thought the iMX6 was a 32 bit addressed processor. Thanks in advance.

00:00.0 PCI bridge: Device 16c3:abcd (rev 01) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Memory at 01a00000 (64-bit, prefetchable) [size=1M]
Bus: primary=00, secondary=01, subordinate=07, sec-latency=0
Memory behind bridge: 01000000-019fffff
[virtual] Expansion ROM at 01b00000 [disabled] [size=64K]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Virtual Channel

Re: IMX6 PCIe Root Complex BAR

weidong_sun — Sun, 22 Jan 2017 10:44:14 GMT

Hello Greg,

i.mx6 driver configures BAR0 & BAR1 to be 64-bit, prefetchable mode. you can refer to the following links:

IMX6 PCIe EP Cannot configure BAR1

https://community.nxp.com/message/349891

Best Regards,

Weidong

Re: IMX6 PCIe Root Complex BAR

GregT — Mon, 23 Jan 2017 16:47:17 GMT

Hi Weidong,

I see where the driver allocates 64-bit BAR when in EP (EndPoint) mode but we do not have that config turned on and pdata->type_ep == 0.

Thanks,

Greg