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    <title>topic Re: Question, i.MX53 LVDS clock in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX53-LVDS-clock/m-p/632534#M96218</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;&lt;SPAN&gt;When LVDS of i.MX53 is used as two output channels, can the output clocks of both channels be different?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;yes&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;&lt;SPAN&gt;please let me know which part of i.MX53, registers, should be configured to make different clocks for dual LVDS out.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;please check description of IOMUXC_GPR2, Table 47-4. Channel Mapping&amp;nbsp; i.MX53 RM&lt;/P&gt;&lt;P&gt;and obds code examples in ../ipu/lvds_out.c&lt;/P&gt;&lt;P&gt;Lab and Test Software (2)&lt;BR /&gt;On-Board Diagnostic Suit for the i.MX53 Quick Start Board (REV 2011.39) &lt;BR /&gt;&lt;A href="http://www.nxp.com/products/power-management/pmics/pmics-for-i.mx-processors/i.mx53-quick-start-board:IMX53QSB?fpsp=1&amp;amp;tab=Design_Tools_Tab"&gt;http://www.nxp.com/products/power-management/pmics/pmics-for-i.mx-processors/i.mx53-quick-start-board:IMX53QSB?fpsp=1&amp;amp;tab=Design_Tools_Tab&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;May be useful i.MX53 System Development User’s Guide &lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fuser_guide%2FMX53UG.pdf" rel="nofollow" target="_blank"&gt;http://www.freescale.com/files/32bit/doc/user_guide/MX53UG.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 13 Oct 2016 23:37:52 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-10-13T23:37:52Z</dc:date>
    <item>
      <title>Question, i.MX53 LVDS clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX53-LVDS-clock/m-p/632533#M96217</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about LVDS output clock of i.MX53.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;When LVDS of i.MX53 is used as two output channels, can the output clocks of both channels be different?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If yes, please let me know which part of i.MX53, registers, should be configured to make different clocks for dual LVDS out.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Oct 2016 13:02:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX53-LVDS-clock/m-p/632533#M96217</guid>
      <dc:creator>Aemj</dc:creator>
      <dc:date>2016-10-13T13:02:50Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX53 LVDS clock</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX53-LVDS-clock/m-p/632534#M96218</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;&lt;SPAN&gt;When LVDS of i.MX53 is used as two output channels, can the output clocks of both channels be different?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;yes&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;&lt;SPAN&gt;please let me know which part of i.MX53, registers, should be configured to make different clocks for dual LVDS out.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;please check description of IOMUXC_GPR2, Table 47-4. Channel Mapping&amp;nbsp; i.MX53 RM&lt;/P&gt;&lt;P&gt;and obds code examples in ../ipu/lvds_out.c&lt;/P&gt;&lt;P&gt;Lab and Test Software (2)&lt;BR /&gt;On-Board Diagnostic Suit for the i.MX53 Quick Start Board (REV 2011.39) &lt;BR /&gt;&lt;A href="http://www.nxp.com/products/power-management/pmics/pmics-for-i.mx-processors/i.mx53-quick-start-board:IMX53QSB?fpsp=1&amp;amp;tab=Design_Tools_Tab"&gt;http://www.nxp.com/products/power-management/pmics/pmics-for-i.mx-processors/i.mx53-quick-start-board:IMX53QSB?fpsp=1&amp;amp;tab=Design_Tools_Tab&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;May be useful i.MX53 System Development User’s Guide &lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fuser_guide%2FMX53UG.pdf" rel="nofollow" target="_blank"&gt;http://www.freescale.com/files/32bit/doc/user_guide/MX53UG.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Oct 2016 23:37:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX53-LVDS-clock/m-p/632534#M96218</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-10-13T23:37:52Z</dc:date>
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