i.MX ProcessorsのトピックSPI Burst Transfer in linux imx6

SPI Burst Transfer in linux imx6

kunalkotecha — Tue, 14 Feb 2017 06:46:36 GMT

Hello all,

I am using imx6ull on a custom board with linux 4.1.15 and currently working on SPI peripheral. I am using IMX6ULL as a Master and DTS for the same is as below :

&ecspi2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio1 29 0>;
   spidev1: spi@1 {
      reg = <0>;
    compatible = "spidev";
      spi-max-frequency = <250000>;
      status = "okay";
   };

};

We used spidev.c as driver for interfacing and did 1 change in it as below:

static const struct of_device_id spidev_dt_ids[] = {
      { .compatible = "rohm,dh2228fv" },
      { .compatible = "spidev" },
      {},
};
and found the device node as /dev/spidev1.0.

It is working properly and able to see pulses of all the pins properly. But We want to transfer more than 1 byte at a time. So in Burst transfer, we are not getting continuous clock pulse and chip select. Hence, at every byte, CS deactivates and then activates again. I tried by cs_change = 0, but still facing issue. Please help me out of it to disable toggling of CS at every byte transfer?

Re: SPI Burst Transfer in linux imx6

igorpadykov — Tue, 14 Feb 2017 08:36:40 GMT

Hi Kunal

please try patch on

spi-imx: imx6q add single burst transfer support - Patchwork

Best regards
igor
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Re: SPI Burst Transfer in linux imx6

константинкисел — Thu, 13 Sep 2018 10:06:11 GMT

Hi, Igor

I applied patch to 4.9.11 kernel and have a problems.

I want to make multiple (from 2 up to 17) bytes burst transfer (tx and rx) but spi output is broken. Data are broken on any transfer with size > 4 and size!=(4*n) in bytes.

When I send 1,2,3,4 in one burst - it ok

When I send 1,2,3,4,5 in one burst - i see 4,0,0,0,5 on SPI output with logic analyzer

When I send 1,2,3,4,5,6 in one burst - i see 3,4,0,0,5,6 on SPI output with logic analyzer