topic Re: IMX6Q Device Tree Binding for ADV7343 Encoder in i.MX Processors

IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Mon, 19 Sep 2016 16:37:29 GMT

Hello all,

We intend to use ADV7343 video encoder with IMX6Q (specifically IMX6Q Sabrelite) parallel RGB interface (DISP_DAT). I need to figure out few things on device tree binding and how to adapt it to this encoder. I am using BD Linux Kernel : boundary-imx_3.14.52_1.1.0_ga and the corresponding dts file has the notations of for adv7180 device :-

pinctrl_i2c3: i2c3grp {
	fsl,pins = <
	MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
	MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
	#define GPIRQ_I2C3_J7 <&gpio1 9 IRQ_TYPE_EDGE_FALLING>
	#define GP_I2C3_J7 <&gpio1 9 GPIO_ACTIVE_LOW>
	MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* I2C3 J7 interrupt */
	>;
	};

	pinctrl_i2c3_adv7180_gpios: i2c3-adv7180_gpiosgrp {
	fsl,pins = <
	/* No data enable pin, make sure it is not selected */
	MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x0b0b1
	#define GP_ADV7180_PWN <&gpio3 13 GPIO_ACTIVE_LOW>
	MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0
	#define GP_ADV7180_RESET <&gpio3 14 GPIO_ACTIVE_LOW>
	MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0
	#define GPIRQ_ADV7180 <&gpio5 0 IRQ_TYPE_LEVEL_LOW>
	MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
	>;
	};

Can some one explain why we have two such nodes for this chip ? Has anyone done this for adv7343 chip ?

Thanks

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

igorpadykov — Mon, 19 Sep 2016 23:59:38 GMT

Hi Anuradha

as adv7343 chip is used instead LCD (not as adv7180 which is sensor),

please check BD blog for various LCDs connections:

https://boundarydevices.com/configuring-i-mx6-machines-different-screens-nitrogen6x-sabre-lite/

so one will have to adapt resolutions and timings for ADV7343.

For dts customizations one can look at

http://boundarydevices.com/mx6-device-tree-customization/

Best regards
igor
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Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Wed, 21 Sep 2016 07:23:57 GMT

Hi Igor and All,

Thanks for your reply. Well I just put the above code to get the DTS notation cleared. I think I have figured out the pinctrl function and how to make an entry for ADV7343 in dts as an i2c node. So the modifications I made (in bold) in my dts (imx6q-sabrelite.dts) file and dtsi file (imx6qdl-sabrelite.dtsi which the dts includes) look like this :

IN IMX6QDL-SABRELITE.DTSI ----->

pinctrl_i2c3_adv7180: i2c3-adv7180grp {
/* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */
};

pinctrl_i2c3_adv7343: i2c3-adv7343grp {

};

aliases {
   backlight_lcd = &backlight_lcd;
   backlight_lvds = &backlight_lvds;
   fb_hdmi = &fb_hdmi;
   fb_lcd = &fb_lcd;
   fb_lvds = &fb_lvds;
   fb_adv7343 = &fb_adv7343;
   lcd = &lcd;
   ldb = &ldb;
   mmc0 = &usdhc3;
   mmc1 = &usdhc4;
   mmc2 = &usdhc2;
   mxcfb0 = &fb_hdmi;
   mxcfb1 = &fb_lvds;
   mxcfb2 = &fb_lcd;
   mxcfb3 = &fb_adv7343;
   pwm_lcd = &pwm1;
   pwm_lvds = &pwm4;
   t_lvds = &t_lvds;
};

fb_lcd: fb@2 {
   compatible = "fsl,mxc_sdc_fb";
   disp_dev = "lcd";
   interface_pix_fmt = "RGB666";
   default_bpp = <16>;
   int_clk = <0>;
   late_init = <0>;
   status = "disabled";
};

fb_adv7343: fb@3 {
   compatible = "fsl,mxc_sdc_fb";
   disp_dev = "adv7343";
   interface_pix_fmt = "RGB24";
   default_bpp = <32>;
   int_clk = <0>;
   late_init = <0>;
   status = "okay";
};

IN IMX6Q-SABRELITE.DTS ----->

&pinctrl_i2c3_adv7343 {
   fsl,pins = <
    MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
   MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
   MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
   MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
   MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
   MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
   MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
   MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
   MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
   MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
   MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
   MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
   MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
   MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
   MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
   MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
   MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
   MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
   MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
   MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
   MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
   MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
   MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
   MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
   MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
   MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
   MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
   MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
   >;
};

&i2c3 {
   clock-frequency = <100000>;
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_i2c3>;
   status = "okay";

   adv7343: adv7343@2D {               //0x2D is I2C address of encoder
         compatible = "adv,adv7343";
         reg = <0x2D>;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c3_adv7343>;
         DOVDD-supply = <&reg_3p3v>; /* 3.3v */
         AVDD-supply = <&reg_3p3v>; /* 3.3v */
         DVDD-supply = <&reg_1p8v>; /* 1.8v */
         PVDD-supply = <&reg_1p8v>; /* 1.8v */
         ipu_id = <0>;
         disp_id = <0>;
         default_ifmt = "RGB24";
         status = "okay";
      };
};

&fb_adv7343 {
status = "okay";
};

This was written assuming that the Parallel RGB to encoder behaves in the same way as a display device (but i am not sure whether this binding is correct). Anyway I am still unable to get the output available. I installed the adv7343 driver as an external module in imx6 and the module is visible under lsmod. Before installing the driver I was also able to communicate to the encoder through raw IMX6 I2C data, so the i2c address seems to be correct. And when the driver module is loaded, the i2c bus gets busy and my assumption is the imx6 is trying to communicate with encoder through the driver. Another thing I am not certain is how to use the fbs (frame buffers I guess) and mxcfbs with this encoder. Any hints on this ?

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Wed, 21 Sep 2016 13:45:30 GMT

Qiang_FSL‌ : Dear Qiang, I saw an excellent post you've made on cvbs output of imx6. Would you be able to give a hint on this ? Can we adapt adv739x for this encoder ?

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

qiang_li-mpu_se — Thu, 22 Sep 2016 02:29:58 GMT

Hi Anuradha Ranasinghe, the adv7343 can work in VSYNC/HSYNC mode, so you can reference to mxc_lcdif.c to create a new fb driver.

Here is an example, IMX6 LCDIF output VSYNC/HSYNC display data to SII902x chip, which will convert the parallel LCD input to HDMI output.

https://community.nxp.com/docs/DOC-329734

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Thu, 22 Sep 2016 05:17:26 GMT

Hi,

Thanks for your input Qiang_FSL‌, I think you had used similar routines in mxcfb_adv739x.c as well. And the both sources are really helpful at this point. But I have to figure out one thing : the available linux driver for adv7343.c has only v4l2 routines (no frame buffer usage) for v4l2-subdev, so does this enumerate the encoder as a video device ? I'm trying to understand how this driver supposes to forward encoder calls. Particularly for my application is this driver usable ?

Thank you all

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Thu, 22 Sep 2016 07:10:08 GMT

I'm referring to this driver :

https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_3.14.52_1.1.0_ga/drivers/media/i2c/adv7343.c

And I noticed this driver has enumerated a /dev/video16 and with command v4l2-ctl -d /dev/video16 -all, I am receiving following output in the terminal :

Driver Info (not using libv4l2):
   Driver name : mxc_vout
   Card type : DISP4 BG
   Bus info :
   Driver version: 3.14.52
   Capabilities : 0x04000002
   Video Output
   Streaming
Format Video Output:
   Width/Height : 320/240
   Pixel Format : ''
   Field : Any
   Bytes per Line: 0
   Size Image : 76800
   Colorspace : Unknown (00000000)
Crop Capability Video Output:
   Bounds : Left 0, Top 0, Width 1280, Height 720
   Default : Left 0, Top 0, Width 1280, Height 720
   Pixel Aspect: 0/0
   horizontal_flip (bool) : default=0 value=0
   vertical_flip (bool) : default=0 value=0
   rotate (int) : min=0 max=270 step=90 default=0 value=0

and for cat /sys/class/graphics/fb0/modes I get various video format information as follows ->

U:1280x720p-60

S:640x480p-60

V:640x480p-60

What I do not understand is how to get this enumerated device work for encoder output and to get the cvbs signal.....

https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_3.14.52_1.1.0_ga/drivers/media/i2c/adv7343.c

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

qiang_li-mpu_se — Thu, 22 Sep 2016 07:22:24 GMT

Hi Anuradha Ranasinghe, if you just reference to this media/i2c/adv7343.c driver, it can't combine with the IPU hardware, so there is no real display output from IMX6 to adv7343. You should reference to the mxcfb_sii902x.c, it is more close to your case.

I don't have the mxcfb_adv739x.c code for 3.14.52 kernel, and this driver is for BT656 interface, it is more complicated on IMX6 IPU side.

In another way, you can just use the current mxc_lcdif.c driver and add your display mode into it, such as 1280*720, then set video mode in boot command as followed, after booted, just config the adv7343 with I2C initialization codes.

video=mxcfb0:dev=lcd, LCD-720P60,if=RGB24,bpp=32

{

/* 1280x720p @ 60 Hz , pixel clk @ 74.25MHz */

"LCD-720P60", 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,

FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

FB_VMODE_NONINTERLACED,

0,},

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Thu, 22 Sep 2016 08:20:07 GMT

Dear Qiang_FSL, Well I thought about that too. So that this initialization code can be placed in our user application to set the encoder settings. But having a driver is genuine though. Thanks alot for your suggestions and support on this. I'll try writing the mxcfb driver for the encoder, Btw do we have other dependencies (files depend on FBs and IPUv3) of assigning mxc_frame buffers for the encoder ? And If I load the modified mxcfb_lcd code or (mxc_adv7343 which I write) and add it as an external driver module, would the driver work or should it be built with kernel ?

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

qiang_li-mpu_se — Fri, 23 Sep 2016 07:34:19 GMT

The module mode driver of mxc_adv7343 is OK too.

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Fri, 23 Sep 2016 08:49:13 GMT

Hi, so I am trying to get the lcd signals directly to RGB port. The configuration settings are given below :

These are my dts information ---->

ipu1 = "/soc/ipu@02800000";
fb_hdmi = "/fb@0";
fb_lcd = "/fb@2";
fb_lvds = "/fb@1";
lcd = "/lcd@0";
ldb = "/soc/aips-bus@02000000/ldb@020e0008";
mxcfb0 = "/fb@0";
mxcfb1 = "/fb@1";
mxcfb2 = "/fb@2";

fb_lcd: fb@2 {
   compatible = "fsl,mxc_sdc_fb";
   disp_dev = "lcd";
   interface_pix_fmt = "RGB24";
   default_bpp = <16>;
   int_clk = <0>;
   late_init = <0>;
   status = "disabled";
};

lcd: lcd@0 {
   compatible = "fsl,lcd";
   ipu_id = <0>;
   disp_id = <0>;
   default_ifmt = "RGB24";
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_lcd0>; //having RGB DISP pins
   status = "okay";
};

And mxc_lcd infor ---->

static struct fb_videomode lcdif_modedb[] = {
{
/* 800x480 @ 57 Hz , pixel clk @ 27MHz */
"CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
FB_SYNC_CLK_LAT_FALL,
FB_VMODE_NONINTERLACED,
0,},

I used following Uboot command to pass the env information :-

=> setenv mmcargs setenv bootargs console=${console},${baudrate} root=${mmcroot} fbmem=24M video=mxcfb2:dev=lcd,CLAA-WVGA,if=RGB24,bpp=32

=> saveenv

=> reset

But there is no signal present at pixel clock output, nor DRDY. Does the RGB port have an auto-detection mechanism for lcd mode ? But as I mentioned at the beginning, the RGB port signals are devoted for encoder chip. My Uboot terminal output at boot is attached herewith.

Thank You

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

qiang_li-mpu_se — Fri, 23 Sep 2016 09:20:55 GMT

On NXP iMX6 SabreSD board:

video=mxcfb0:dev=lcd,CLAA-WVGA,if=RGB565,bpp=32

In device tree file "arch\arm\boot\dts\imx6qdl-sabresd.dtsi", it is on IPU0 DI0 since the display PINs are on this interface:

lcd@0 {
  compatible = "fsl,lcd";
  ipu_id = <0>;
  disp_id = <0>;
  default_ifmt = "RGB565";
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_ipu1>;
  status = "okay";
};

  pinctrl_ipu1: ipu1grp {
   fsl,pins = <
    MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
    MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
    MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
    MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
    MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
    MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
    MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
    MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
    MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
    MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
    MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
    MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
    MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
    MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
    MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
    MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
    MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
    MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
    MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
    MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
    MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
    MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
    MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
    MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
    MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
    MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
    MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
    MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
    MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
   >;
  };

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Fri, 23 Sep 2016 11:22:18 GMT

Exactly Qiang_FSL‌, sorry I missed that part in my previous comment. pincntrl looks like this (but having a different grp name). And I also included MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 to the grp :

pinctrl_lcd0: lcd0grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};

and changed lcd@ as follows (from original sabrelite dts/dtsi and for that particular display the format is set to RGB666)

lcd: lcd@0 {
   compatible = "fsl,lcd";
   ipu_id = <0>;
   disp_id = <0>;
   default_ifmt = "RGB666";
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_lcd0>; //having RGB DISP pins
   status = "okay";
};

So basically settings look okay except the DI0_PIN4. But still I cannot detect a sensible signal from pixel clk, but strangely when I am in the Uboot through console, following signals (in attachment) were acquired from DRDR (Red) and DISP0_CLK (Blue). What could be the reason for this :

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

qiang_li-mpu_se — Tue, 27 Sep 2016 05:26:14 GMT

DI0_PIN4 is not used.

Maybe you had set lcd to second framebuffer, so it is blanked default.

Please attached your full kernel boot up log. And after booted into Linux, please run the followed commands to dump the display informamtions:

$ cat /sys/class/graphics/fb0/fsl_disp_dev_property

$ cat /sys/class/graphics/fb1/fsl_disp_dev_property

$ cat /sys/class/graphics/fb2/fsl_disp_dev_property

$ cat /sys/class/graphics/fb3/fsl_disp_dev_property

$ cat /sys/class/graphics/fb4/fsl_disp_dev_property

$ cat /sys/class/graphics/fb5/fsl_disp_dev_property

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Wed, 28 Sep 2016 06:40:04 GMT

Dear Qing,

Hi, the frame buffer assignment issue was in the 6x_bootscript file, as it is loaded after the uboot command and it overwrites whatever I specified with uboot commands. After adding the video command (setenv bootargs ${bootargs} video=mxcfb0:dev=lcd,CLAA-WVGA,if=RGB24,bpp=32) to 6x_bootscript, I was able to get sort of acceptable signal wave forms from the RGB port. Now the terminal outputs for the above cat commands look like this :

> cat /sys/class/graphics/fb0/fsl_disp_dev_property
> lcd //----------------------------------------- > so fb0 is assigned to our lcd, this must be okay right ?
> root@tengri:/home/ubuntu# cat /sys/class/graphics/fb1/fsl_disp_dev_property
> overlay
> root@tengri:/home/ubuntu# cat /sys/class/graphics/fb2/fsl_disp_dev_property
> cat: /sys/class/graphics/fb2/fsl_disp_dev_property: No such file or directory

And after the i2c settings, I received sort of a cvbs looking signal from the encoder. However the TV does not detect this cvbs signal. I have few doubts about the settings I am using and they are as follows :

--------- DTS Settings ---------

1. pincntrl settings of the lcd are defines as exactly as the way you pointed out (including DI0_PIN4).

2. lcd: lcd@0 {
      compatible = "fsl,lcd";
      ipu_id = <0>;
      disp_id = <0>;
      default_ifmt = "RGB24";         //This was originally RGB666 in default dts, is it okay to change this to RGB24 ?
      pinctrl-names = "default";
      pinctrl-0 = <&pinctrl_lcd0>;
      status = "okay";
};

--------- 6x_bootscript ----------

setenv bootargs ${bootargs} video=mxcfb0:dev=lcd,CLAA-WVGA,if=RGB24,bpp=32

--------- But in mxc_lcdif.c ----------

{
/* 800x480 @ 57 Hz , pixel clk @ 27MHz */
"CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
FB_SYNC_CLK_LAT_FALL,
FB_VMODE_NONINTERLACED,
0,},
{

I know this settings in the lcdif is not compatible with the device (in video command) I have used. But instead of compiling the whole kernel (as this is a built in driver, external module installation can't be done) can't we pass following parameters in the boot command ? Specially the command FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, ?

/* 1280x720p @ 60 Hz , pixel clk @ 74.25MHz */

"LCD-720P60", 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,

FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

FB_VMODE_NONINTERLACED,

0,},

I've also attached the wave forms observed herewith, I'd be really grateful if you could take a look at them and advise me.....

Thanks in advance !

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Thu, 06 Oct 2016 16:52:38 GMT

Dear Qiang Li,

Hi, I was able to detect a video signal with VSYNC/HSYNC mode after modifying the lcd code, now I have few questions about the video format of the lcd entry.

1. Should MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 be used in LCD group in dts file ?

2. Since we are receiving signals from 24 bit RGB port, what should be correct settings of lcd@ in dts file ?

lcd: lcd@0 {
   compatible = "fsl,lcd";
   ipu_id = <0>;
   disp_id = <0>;
   default_ifmt = "RGB666"; //shouldn't this be RGB24 ?
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_lcd0>;
   status = "okay";
};

3. The adv7343 encoder provides cvbs output only for an SD video input (or since any input is coming 24 bit format, should this work?) so if we modify the lcd entry of mxc_lcdif.c for that, how does it look like ?

/* 1280x720p @ 60 Hz , pixel clk @ 74.25MHz */

"LCD-720P60", 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,

FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

FB_VMODE_NONINTERLACED,

0,},

I'd be grateful if you could kindly answer these question, one by one.......

Thanks in advance !

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

qiang_li-mpu_se — Sat, 08 Oct 2016 02:21:36 GMT

For Q1, DI0_PIN4 is not needed, your hardware doesn't need use it.

For Q2, the ifmt depends on your hardware, for NXP reference board, we only connected 18 data lines to LCD panel, so it is RGB666, if your hardware had connected 24 data lines, then you should use RGB24.

For Q3, that LCD-720P60 timing parameters is from CEA-861-D specification, you can check the SD video timing with adv7343.

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Mon, 16 Jan 2017 10:52:30 GMT

Dear Qian Li,

Hi, apart from the entry in mxc_lcdif.c, do I need to change settings in any other source files (i.e. ipu_disp.c ) to get this work ? After compiling the kernel, the pixel clock of IPU1DISP0 becomes 38MHz instead of SD 27MHz. I checked the imx6_clk.c file, the parent of the DISP0 is set to PLL5. The pixel clock value is similarly wrong for the CLAA-WVGA lcd ! what could cause this issue ?

and in mxc_lcdif.c
/* 800×480 @ 57 Hz , pixel clk @ 27MHz */
TENGRI-LCD”, 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT
FB_VMODE_NONINTERLACED,
0,},

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

tengri — Mon, 16 Jan 2017 12:25:59 GMT

And for this FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, following are the HSYNC and VSYNC acquired at RGB port. Can you please verify these two signals ? :

Blue : HSYNC and RED : VSYNC

Anyway the encoded signal I have at cvbs output does not have color space, only leaving the color burst in the signal !!!

Re: IMX6Q Device Tree Binding for ADV7343 Encoder

qiang_li-mpu_se — Thu, 19 Jan 2017 02:30:41 GMT

Can you run command "cat /sys/kernel/debug/clk/clk_summary" to dump the real clock tree setting? Maybe you had set the pixel clock to IPU internal clock mode.

Please check device tree and make sure int_clk is 0:

mxcfb3: fb@x {
  compatible = "fsl,mxc_sdc_fb";
  disp_dev = "lcd";
  interface_pix_fmt = "RGB565";
  mode_str ="CLAA-WVGA";
  default_bpp = <16>;
  int_clk = <0>;
  late_init = <0>;
  status = "disabled";
};