iMX6UL Reference Manual - DDR density specification

markusb — Thu, 19 Jan 2017 08:11:49 GMT

Hi,

in IMX6ULRM it say in 33.1.1 , that 256Mbits-8Gbits are the supported densities of DDR devices, however 6.2 specifies a density of 256Mbytes - 4Gbytes.

I suppose the first one is correct and there would be no issue using a 128MByte = 1Gbit device?

Thanks!

Re: iMX6UL Reference Manual - DDR density specification

Yuri — Fri, 20 Jan 2017 04:35:21 GMT

Hello,

The i.MX6UL MMDC inludes the following features :

* x16 data bus width (2 bytes);

* up to 8 banks (3 bits );

* column size of 8–12 bits ;

* row size of 11–16 bits.

So, minimal address size is 8 MBytes [2 ** (11+8+3+1)]

and maximal one is full 4GB.

128 MB is supported.

Have a great day,
Yuri

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topic iMX6UL Reference Manual - DDR density specification in i.MX Processors

iMX6UL Reference Manual - DDR density specification

Re: iMX6UL Reference Manual - DDR density specification