<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: Reading Keypad Data Register crashes i.MX 7 SoC</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Reading-Keypad-Data-Register-crashes-i-MX-7-SoC/m-p/628989#M95494</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hm, I first thought of clocks, too, but checked the gate mentioned in Chapter 5,&amp;nbsp;Table 5-12:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE class="j-table jiveBorder" style="border: 1px solid #c6c6c6;" width="100%"&gt;&lt;THEAD&gt;&lt;TR style="background-color: #efefef;"&gt;&lt;TH&gt;Module&lt;/TH&gt;&lt;TH&gt;Module Clock (instance.clock)&lt;/TH&gt;&lt;TH&gt;Clock Root&lt;/TH&gt;&lt;TH&gt;Module Clock Gating&lt;BR /&gt;Enable (CCGR)&lt;/TH&gt;&lt;/TR&gt;&lt;/THEAD&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;KPP&lt;/TD&gt;&lt;TD&gt;kpp.ipg_clk_s&lt;/TD&gt;&lt;TD&gt;IPG_CLK_ROOT&lt;/TD&gt;&lt;TD&gt;clk_enable_kpp (&lt;SPAN style="color: #ff0000;"&gt;CCGR120&lt;/SPAN&gt;)&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So after&amp;nbsp;checking CCGR120, I was convinced that clocking is fine, especially since the rest of the registers seemed to work...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Anyway, now after enabling the correct gate, CCGR170, the&amp;nbsp;register at offset 6 is readable too!&amp;nbsp;I guess CCGR120 in the table above&amp;nbsp;is an error in the reference manual....&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Stefan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 29 Nov 2016 18:46:06 GMT</pubDate>
    <dc:creator>falstaff</dc:creator>
    <dc:date>2016-11-29T18:46:06Z</dc:date>
    <item>
      <title>Reading Keypad Data Register crashes i.MX 7 SoC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Reading-Keypad-Data-Register-crashes-i-MX-7-SoC/m-p/628987#M95492</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our customer discovered a kernel freeze when trying to initialize the Keypad driver in Linux. Looking a bit closer in why it exactly freezes we could pinpoint a single register read during the drivers initialization: In&amp;nbsp;&lt;EM&gt;imx_keypad_config&lt;/EM&gt; the driver &lt;SPAN style="text-decoration: underline;"&gt;reads&lt;/SPAN&gt; the&amp;nbsp;Keypad Data Register (KPDR) on which line the system freezes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;PRE&gt;
static void imx_keypad_config(struct imx_keypad *keypad)
{
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; unsigned short reg_val;

&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; * Include enabled rows in interrupt generation (KPCR[7:0])
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; * Configure keypad columns as open-drain (KPCR[15:8])
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg_val = readw(keypad-&amp;gt;mmio_base + KPCR);
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg_val |= keypad-&amp;gt;rows_en_mask &amp;amp; 0xff; /* rows */
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg_val |= (keypad-&amp;gt;cols_en_mask &amp;amp; 0xff) &amp;lt;&amp;lt; 8; /* cols */
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; writew(reg_val, keypad-&amp;gt;mmio_base + KPCR);

&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Write 0's to KPDR[15:8] (Colums) */
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;STRONG&gt;reg_val = readw(keypad-&amp;gt;mmio_base + KPDR);&amp;lt;FREEZE&amp;gt;&lt;/STRONG&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg_val &amp;amp;= 0x00ff;
&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; writew(reg_val, keypad-&amp;gt;mmio_base + KPDR);

&lt;/PRE&gt;&lt;P&gt;We can also verify that with a simple read using U-Boot.. Other register in the same block seem to work fine:&lt;/P&gt;&lt;PRE&gt;=&amp;gt; md.w 0x30320004 1
30320004: 0000 ..
=&amp;gt; md.w 0x30320002 1
30320002: 0002 ..
=&amp;gt; md.w 0x30320006 1
30320006:&amp;lt;FREEZE&amp;gt;&lt;/PRE&gt;&lt;P&gt;As far as I understand there should be no limitations on when this register is readable. It is only byte or half-word addressable, and md.&lt;STRONG&gt;w&lt;/STRONG&gt; is addressing it using a half-word read, so this should be a valid register access.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This is&amp;nbsp;reproducible on our Colibri iMX7 modules as well as on a NXP MCIMX7SABRE Rev. C (mask&amp;nbsp;2N09P). I did not found a related errata.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Stefan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Nov 2016 21:22:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Reading-Keypad-Data-Register-crashes-i-MX-7-SoC/m-p/628987#M95492</guid>
      <dc:creator>falstaff</dc:creator>
      <dc:date>2016-11-28T21:22:30Z</dc:date>
    </item>
    <item>
      <title>Re: Reading Keypad Data Register crashes i.MX 7 SoC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Reading-Keypad-Data-Register-crashes-i-MX-7-SoC/m-p/628988#M95493</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Stefan&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;usually hanging occurs due to clock absence, so one can check&lt;/P&gt;&lt;P&gt;if kpp clock is gated, please check CCM_CCGR170 Table 5-19. CCGR Mapping Table&amp;nbsp;&lt;/P&gt;&lt;P&gt;i.MX7D Reference Manual&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf"&gt;http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Additionally RDC module can impose access restrictions.&lt;/P&gt;&lt;P&gt;It may be useful to check read/write with jtag.&lt;/P&gt;&lt;P&gt;In linux one can look at kpp imx6sl-evk.dts&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts/imx6sl-evk.dts?h=imx_4.1.15_1.0.0_ga" title="http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts/imx6sl-evk.dts?h=imx_4.1.15_1.0.0_ga"&gt;linux-2.6-imx.git - Freescale i.MX Linux Tree&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Nov 2016 06:35:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Reading-Keypad-Data-Register-crashes-i-MX-7-SoC/m-p/628988#M95493</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-11-29T06:35:11Z</dc:date>
    </item>
    <item>
      <title>Re: Reading Keypad Data Register crashes i.MX 7 SoC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Reading-Keypad-Data-Register-crashes-i-MX-7-SoC/m-p/628989#M95494</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hm, I first thought of clocks, too, but checked the gate mentioned in Chapter 5,&amp;nbsp;Table 5-12:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE class="j-table jiveBorder" style="border: 1px solid #c6c6c6;" width="100%"&gt;&lt;THEAD&gt;&lt;TR style="background-color: #efefef;"&gt;&lt;TH&gt;Module&lt;/TH&gt;&lt;TH&gt;Module Clock (instance.clock)&lt;/TH&gt;&lt;TH&gt;Clock Root&lt;/TH&gt;&lt;TH&gt;Module Clock Gating&lt;BR /&gt;Enable (CCGR)&lt;/TH&gt;&lt;/TR&gt;&lt;/THEAD&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;KPP&lt;/TD&gt;&lt;TD&gt;kpp.ipg_clk_s&lt;/TD&gt;&lt;TD&gt;IPG_CLK_ROOT&lt;/TD&gt;&lt;TD&gt;clk_enable_kpp (&lt;SPAN style="color: #ff0000;"&gt;CCGR120&lt;/SPAN&gt;)&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So after&amp;nbsp;checking CCGR120, I was convinced that clocking is fine, especially since the rest of the registers seemed to work...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Anyway, now after enabling the correct gate, CCGR170, the&amp;nbsp;register at offset 6 is readable too!&amp;nbsp;I guess CCGR120 in the table above&amp;nbsp;is an error in the reference manual....&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Stefan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Nov 2016 18:46:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Reading-Keypad-Data-Register-crashes-i-MX-7-SoC/m-p/628989#M95494</guid>
      <dc:creator>falstaff</dc:creator>
      <dc:date>2016-11-29T18:46:06Z</dc:date>
    </item>
    <item>
      <title>Re: Reading Keypad Data Register crashes i.MX 7 SoC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Reading-Keypad-Data-Register-crashes-i-MX-7-SoC/m-p/628990#M95495</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;All,&lt;/P&gt;&lt;P&gt;Thank you for finding and pointing out the errors in the reference manual. I do want to point you to table 5-19 which is the CCGR Mapping Table, which shows CCM_CCGR_170 for the KPP module.&lt;/P&gt;&lt;P&gt;It appears the correct data is shown in table 5-19 and incorrect in table 5-12. I have made the corrections in our systems.&lt;/P&gt;&lt;P&gt;thanks again,&lt;/P&gt;&lt;P&gt;mark&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Nov 2016 22:01:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Reading-Keypad-Data-Register-crashes-i-MX-7-SoC/m-p/628990#M95495</guid>
      <dc:creator>markruthenbeck</dc:creator>
      <dc:date>2016-11-29T22:01:48Z</dc:date>
    </item>
  </channel>
</rss>

