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    <title>topic Re: DDR3L routing in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628849#M95460</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Surendra&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;As shown in attached figure, does the bigger red circle represent minimum routing length should be Clock(min)-200mil?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;no&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;Does the dash --- represents the same recommendation to DRAM_D[15:8] are&amp;nbsp;same as DRAM_D[7:0].&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;no&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 18 Jan 2017 23:29:51 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-01-18T23:29:51Z</dc:date>
    <item>
      <title>DDR3L routing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628847#M95458</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;We are routing DDR3L signals and referring to HW development guide. In this we are routing the signals as per table, which is attached.&lt;/P&gt;&lt;P&gt;As shown in attached figure, does the bigger red circle represent minimum routing length should be Clock(min)-200mil?&lt;/P&gt;&lt;P&gt;As we are routing clock with 1400 mils, so we are allowed to route data and its control signals between 1200 to 1400 mils?&lt;/P&gt;&lt;P&gt;The other doubt is in smaller red circle. Does the dash --- represents the same recommendation to DRAM_D[15:8] are&amp;nbsp;same as DRAM_D[7:0].&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Surendra J.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Jan 2017 15:10:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628847#M95458</guid>
      <dc:creator>surendrajadhav</dc:creator>
      <dc:date>2017-01-18T15:10:49Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L routing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628848#M95459</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;HI Surendra,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;which processor are you using?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Carlos&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Jan 2017 16:45:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628848#M95459</guid>
      <dc:creator>Carlos_Musich</dc:creator>
      <dc:date>2017-01-18T16:45:55Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L routing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628849#M95460</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Surendra&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;As shown in attached figure, does the bigger red circle represent minimum routing length should be Clock(min)-200mil?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;no&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;Does the dash --- represents the same recommendation to DRAM_D[15:8] are&amp;nbsp;same as DRAM_D[7:0].&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;no&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Jan 2017 23:29:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628849#M95460</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-01-18T23:29:51Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L routing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628850#M95461</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;This question is for i.MX6UL processor.&lt;/P&gt;&lt;P&gt;@Igor,&lt;/P&gt;&lt;P&gt;Thanks a lot for your reply.&lt;/P&gt;&lt;P&gt;Could you please elaborate then what dash represents in the two red circles?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Surendra&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Jan 2017 03:10:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628850#M95461</guid>
      <dc:creator>surendrajadhav</dc:creator>
      <dc:date>2017-01-20T03:10:16Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3L routing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628851#M95462</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Surendra&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;dash represents no specific restrictions/recommendations.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Jan 2017 03:27:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3L-routing/m-p/628851#M95462</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-01-20T03:27:08Z</dc:date>
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