i.MX ProcessorsのトピックMemory controller setup for i.MX28 and i.MX50

Memory controller setup for i.MX28 and i.MX50

VladanJovanovic — Wed, 12 Sep 2012 07:46:48 GMT

Attached are files that will help with setting up i.MX28 and i.MX50 memory controller for different memory types.

Vladan

Original Attachment has been moved to: MX28_mDDR_register_programming_aid_v0.4.zip

Original Attachment has been moved to: MX50_DRAM_controller_register_programming_aid.zip

Re: Memory controller setup for i.MX28 and i.MX50

rohith1z — Fri, 09 Nov 2012 05:53:51 GMT

Is there a similar guide for imx25?

I'm working on supporting 256MB RAM (mddr) for this chipset and not sure if it's supports it.

section 24.1.9 of imx25 reference manual says Up to "128 Mbytes per chip select"

Re: Memory controller setup for i.MX28 and i.MX50

Yuri — Fri, 09 Nov 2012 09:43:12 GMT

SDRAM controller of the i.MX25 is relatively simple (when considering i.MX28 and i.MX50 ones),
nevertheless, the enclosed Excel example - hope - helps.

Re: Memory controller setup for i.MX28 and i.MX50

rohith1z — Mon, 12 Nov 2012 01:26:06 GMT

Thx for the quick response.

In particular I wanted to know if 256M of RAM is supported on a single chip select by mx25(I'm using a 4bank 16*16M ) H5MS1G62MFP-E3M

Re: Memory controller setup for i.MX28 and i.MX50

Yuri — Tue, 13 Nov 2012 09:01:44 GMT

I am afraid this is impossible to have 256 Mbytes with i.MX25, using single chip select.

There are the next restrictions of i.MX25 memory controller :

1) i.MX25 only can support 4-banks ;

2) i.MX25 has a 16-bit data bus ;

3) maximum Row address width is 14 bit ;

4) maximum Column address width is 10 bit.

This means maximum 128 Mbytes per CS.

Re: Memory controller setup for i.MX28 and i.MX50

jschoen — Thu, 28 Mar 2013 16:00:32 GMT

Is there a similar ddr initialization aid for i.MX28 interfacing to DDR2?

I'm particularly interested in setting of HW_DRAM_CTL176 and how those should be set relative to Taond, Taofd, Taofpd, Taonpd, Tanpd, etc from the ddr2 datasheet.

Re: Memory controller setup for i.MX28 and i.MX50

Yuri — Fri, 29 Mar 2013 04:22:19 GMT

Please try the enclosed.

Re: Memory controller setup for i.MX28 and i.MX50

nobuyukitanaka — Fri, 27 Jun 2014 06:51:28 GMT

Is it correct in DQS_N_EN=1?

I think mDDR to be Single-ended DQS.

Memory controller setup for i.MX28

mliang — Wed, 25 Apr 2018 14:00:52 GMT

Hello,

I came across this discussion while searching for MX28 DDR2 register programming file.

We have 4 Micron MT47H256M8EB-25EIT on our board, total 1GByte, and running at about 130MHz.

Currently we have some issues with our board. We suspect it's the DDR2 memory issue and could be related to register setting.

I have setup the attached register programming file. Can anyone please help and check to see if I have the registers setup correctly?

Re: Memory controller setup for i.MX28 and i.MX50

Yuri — Thu, 26 Apr 2018 07:12:16 GMT

Hello,

I think, it makes sense to create separate request (to check memory configuration; also, please attach
(CPU <-> DRAM) schematic).

https://community.nxp.com/docs/DOC-329745

Regards,

Yuri.