i.MX ProcessorsのトピックRe: NAND Flash on iMX53

NAND Flash on iMX53

jomeke — Thu, 24 Nov 2011 13:31:36 GMT

Hi guys,

is there anybody who has a desin example from a NAND flash connected to the iMX537 ?

Re: NAND Flash on iMX53

FlorentAuger — Thu, 24 Nov 2011 17:21:00 GMT

The connection is quite straight. You can use the reference manual of the i.MX53 / table 5-3 at section 5.3.4.

You'll find there that the NAND control signals are dedicated pins with the same name.

Nevertheless, the data bus is not dedicated, and can be used on the PATA signals or EIM data signals.

At boot, it is important to let the processor knows where to use the data bus, and the table 7-14 at section 7.5.2.4 explains this.

You can check that board for a reference:

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX53SABREAUTO&fpsp=1&tab=Design_Tools_Tab

Re: NAND Flash on iMX53

jomeke — Fri, 25 Nov 2011 07:13:20 GMT

Thanks for the information Florent

Florent Auger said:

Hi

The connection is quite straight. You can use the reference manual of the i.MX53 / table 5-3 at section 5.3.4.
You'll find there that the NAND control signals are dedicated pins with the same name.
Nevertheless, the data bus is not dedicated, and can be used on the PATA signals or EIM data signals.

At boot, it is important to let the processor knows where to use the data bus, and the table 7-14 at section 7.5.2.4 explains this.

You can check that board for a reference:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIM...

Re: NAND Flash on iMX53

hoanghoa — Fri, 30 Nov 2012 03:16:24 GMT

Hi guys,

I am porting u-boot for an mx53 board which has 512 MB Nand flash of Samsung K9F4G08.

It uses CS0 and 8 bit interface only. So which value should be for CONFIG_SYS_NAND_BASE?

The connection signal is below:

- NANDF_CS0 --> CS (to NAND chip)

- NANDF_CS1,2,3 --> not used

- PATA_DATA[0-7] --> DATA[0-7]

Expecting your help!!

HTH