i.MX Processors中的主题 Re: IPU Restrictions on Frame width and Height ??

IPU Restrictions on Frame width and Height ??

titusstalin — Wed, 18 Jan 2017 06:05:55 GMT

Dear All,

I am working with MIPI camera which stream the frames in any resolution say 12x12, 800x600, 640x480, 1200x1200 etc.,

I'm able to get the frame 1200x1200 data perfectly, but I'm not able to get the data 1204x1204 resolution.

What could be the problem ?

BTW, my driver is configured in SMFC mode (i.e IC block is not used)

That is "CSI <-> MEM" configuration used.

Any restriction is there to have width and height should be in multiples of 8 and it should be dividable by 4 ?

These are handled in "ipu_init_channel_buffer" function "drivers/mxc/ipu3/ipu_common.c"

Can you please point out in reference manual if any restrictions available like that ?

I've referred CPMEM register, in that I saw "Frame height" and "Frame width" but its not mentioned to be multiples of 8 like that.

Can you please clarify ?

Thanks for your support so far.

Regards,

Titus S

Re: IPU Restrictions on Frame width and Height ??

art — Thu, 26 Jan 2017 11:23:35 GMT

There is no restricition in frame width or height within IPU. The possible cause of the issue is some wrong interface/IPU configuration, since the MIPI-CSI2 -> Gasket -> CSI -> IDMAC -> MEM chain is quite complicated in configuration and setup. Please follow the "MIPI–CSI2 Peripheral on i.MX6 MPUs" AN5305 Application Note document to check your camera/interface/IPU configuration. The document is available on the processor's Documentation web page (check the "Application Notes" section):

http://www.nxp.com/products/automotive-products/microcontrollers-and-processors/arm-mcus-and-mpus/i.mx-application-processors/i.mx-6-processors/i.mx-6quad-processors-high-performance-3d-graphics-hd-video-arm-cortex-a9-core:i.MX6Q?tab=Documentation_Tab

Have a great day,
Artur

Re: IPU Restrictions on Frame width and Height ??

titusstalin — Fri, 27 Jan 2017 04:09:49 GMT

Thanks Artur.

since the MIPI-CSI2 -> Gasket -> CSI -> IDMAC -> MEM chain is quite complicated in configuration and setup.

If that's the case, it should not work for any resolution and as I said, some restriciton is there in code also. Why ?

Any restriction is there to have width and height should be in multiples of 8 and it should be dividable by 4 ?

These are handled in "ipu_init_channel_buffer" function "drivers/mxc/ipu3/ipu_common.c"

If still you are doubt about our register configuration settings, then can you please tell what are the registers need to check ?

I've modified the registers for camera based on clock, (DPHY registers), lanes count, vc settings, data format/type etc.,

Can you please help me on this ?