topic Re: BT.656 Camera Input in i.MX Processors

BT.656 Camera Input

pierre-olivierh — Tue, 11 Oct 2016 09:33:15 GMT

Hello,

We are currently trying to make the BT.656 mode works on a iMX6Q. We use a custom driver, a custom baord, with a SOM.

I will explain all the configuration done, and the errors recieved:

On the .dtsi file :

        pinctrl_ipu2_csi1: ipu1grp-csi0 {
            fsl,pins = <
                MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19        0xb0b1      // Y/C[0]
                MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18        0xb0b1      // Y/C[1]
                MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17        0xb0b1      // Y/C[2]
                MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16        0xb0b1      // Y/C[3]
                MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15        0xb0b1      // Y/C[4]
                MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14        0xb0b1      // Y/C[5]
                MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13        0xb0b1      // Y/C[6]
                MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12        0xb0b1      // Y/C[7]
                MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK        0xb0b1      // Clk
                //DATA_EN pin
                MX6QDL_PAD_EIM_DA10__GPIO3_IO10         PAD_CTRL_HYS_PU
                //Unused
                MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC    PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC    PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04    PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05    PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06    PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07    PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08    PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09    PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10    PAD_CTRL_HYS_PD
                MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11    PAD_CTRL_HYS_PD
               >;
        };

We are using the BT656 pins, (DATA19 to DATA12), other pins are declared but set in pull down, DATA_EN is set in pull-up, our fpga on the board, also set a +3V3 on this pin.

In the .dts:

v4l2_cap_0 {
   compatible = "fsl,imx6q-v4l2-capture";
   ipu_id = <0>;
   csi_id = <1>;
mclk_source = <0>;
      status = "okay";
};
driver {
   compatible = "driver,driver_camera";
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_ipu2_csi1 &pinctrl_cam0_gpio>;
   clocks = <&clks 200>;
   clock-names = "csi_mclk";
   csi_id = <1>;
   mclk = <148500000>;
   mclk_source = <0>;
   power-gpio = <&gpio3 19 0>;
   status = "okay";
};

A FPGA is connected to the CSI pins, the FPGA seems to send valid data, with embedded sync.

Our driver works with mxc_v4l2_capture, and sets the following parametters:

.if_type = V4L2_IF_TYPE_BT656_PROGRESSIVE,
.mode = V4L2_IF_TYPE_BT656_MODE_BT_8BIT,
.bt_sync_correct = 0,
.nobt_vs_inv = 0,
.nobt_hs_inv = 0,
.pixelformat = V4L2_PIX_FMT_YUYV,

I put some debug in drivers/mxc/ipu_capture.c, when I run a pipeline I get the CSI registers :

[ 107.782327] CSI_SENS_CONF = 0x00000920
[ 107.786096] CSI_SENS_FRM_SIZE = 0x0437077F
[ 107.790197] CSI_ACT_FRM_SIZE = 0x0437077F
[ 107.794227] CSI_OUT_FRM_CTRL = 0x00000000
[ 107.798241] CSI_TST_CTRL = 0x00000000
[ 107.801906] CSI_CCIR_CODE_1 = 0x00040030
[ 107.805846] CSI_CCIR_CODE_2 = 0x00000000
[ 107.809773] CSI_CCIR_CODE_3 = 0x00FF0000

The CSI is in BT656, 8bpp, YUYV. 1920*1080, with the FF0000 embedded sync.

When the driver start :

[ 6.098746] mxc_v4l2_master_attach: ipu0:/csi1 parallel attached driver:mxc_v4l2_cap0

I think I have something wrong, I use IPU2 but mxc_v4l2 says I'm using IPU0, how do I change this? I tried to modify the ipu_id in the dts, but the slave is not found.

Also, when I run a gstreamer pipeline, I get a ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

I'm on 3.14 kernel, building images with Yocto, on poky branch.

Thanks for the Help,

Best regards,

Pierre-Olivier

Re: BT.656 Camera Input

igorpadykov — Tue, 11 Oct 2016 23:22:59 GMT

Hi Pierre-Olivier

for progressive BT.656 camera input one can look at below threads

https://community.nxp.com/thread/328880
https://community.nxp.com/thread/300234
https://community.nxp.com/thread/314211

ipu_id is configured in gpr1 register, one can try to debug it using

sect.6.3 Source Code Structure attached Linux Manual.

Best regards
igor
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Re: BT.656 Camera Input

pierre-olivierh — Wed, 12 Oct 2016 08:16:48 GMT

Hi, Thanks for the answer,

I tried to modify my DTS, I use IPU2_CSI1 so :

v4l2_cap_0 {
   compatible = "fsl,imx6q-v4l2-capture";
   ipu_id = <1>; // instead of 0;
   csi_id = <1>;
mclk_source = <0>;
      status = "okay";
};

I also modified the mach-imx.c, adding regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 20, 1 << 20);

I checked, and this register is set, but when my driver starts :

[ 5.959969] mxc_v4l2_master_attach: ipu(0:1)/csi(1:1)/mipi(0:0) doesn't match

Ths slave IPU is 0(so IPU1), and master is 1(IPU2).

Where do I set the slave IPU correctly?

EDIT

I forgot to add the ipu_id in my driver, now I have [ 6.128704] mxc_v4l2_master_attach: ipu1:/csi1 parallel attached driver:mxc_v4l2_cap0

But When I run a gstreamer pipeline : [ 37.363757] ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0
Or when I do a cat /dev/video0 :

[ 440.503757] ERROR: v4l2 capture: mxc_v4l_read timeout counter 0
[ 440.509721] imx-ipuv3 2800000.ipu: Not a CSI channel
cat: read error: Timer expired

Any thoughts?

Re: BT.656 Camera Input

igorpadykov — Wed, 12 Oct 2016 10:40:04 GMT

suggest first to check with imx-test (suggested links give examples of usage),

folder ../mxc_v4l2_test

www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-test-5.4.tar.gz

http://patches.openembedded.org/patch/110753/

Re: BT.656 Camera Input

pierre-olivierh — Wed, 12 Oct 2016 13:14:32 GMT

I'm trying to build it with Yocto, but I get errors (I'm on Poky branch) when I add it to my image.

I tried to add the recipe for imx-test on Jethro branch, it compiles, but I only have the scripts, the binaries are not on my rootfs (mxc_v4l2_capture.out for example)

Re: BT.656 Camera Input

pierre-olivierh — Fri, 14 Oct 2016 11:11:10 GMT

I checked some registers :

- IOMUXC_GPR1 bit 20 is set to 1 ( ipu2 connected to CSI1 not MIPI)

- IPUx_CONF is set to 0x80000002 -> CSI1 enabled and selected

- CCM_CCGR3 : 0x3ff3000f ->Clock of IPU2 not enabled, I tried to write 0x3ff30fff but it does not work. (I think this register is only for display)

- I removed the DATA_EN pin from the DTSI, as seen on this forum.

- I checked all the Pins, all are set to the right values, the daisy chain is set too.

- I tried to put IPU in TEST MODE, CSI_TEST_CTRL set to 0x01000000

With all these modifications, I still get ERROR: v4l2 capture: mxc_v4l_read timeout counter 0.

Any Thoughts?

EDIT:

I set CCM_CCGR3 register ipu2_ipu_clk_enable to 0x11 (always on), but when I load my driver, this register come back to 0x3ff3000f (disbaling the ipu2 clk)

Is this normal? I do not touch it in my driver.

EDIT2:

The configuration is right, SAV/EAV were in bad format.