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    <title>i.MX ProcessorsのトピックRe: DDR CS1 Boot</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DDR-CS1-Boot/m-p/623312#M94535</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Vishakh&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for configuration of CS0 and CS1 address space with 2GB one can refer to&lt;/P&gt;&lt;P&gt;arm2 board (sch-27016)&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/329819"&gt;i.MX6Q/DL 4GB DDR3 RAM porting&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/431885"&gt;IMX6 surpport 4GB DDR3 reference BRD and length excel&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;L4.1.15 arm2 dts file: imx6q-arm2.dts&lt;BR /&gt;git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts/imx6q-arm2.dts?h=imx_4.1.15_1.0.0_ga&lt;BR /&gt;uboot imx_v2015.04 *.cgf file&lt;BR /&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fgit.freescale.com%2Fgit%2Fcgit.cgi%2Fimx%2Fuboot-imx.git%2Ftree%2Fboard%2Ffreescale%2Fmx6qarm2%3Fh%3Dimx_v2015.04_4.1.15_1.0.0_ga" rel="nofollow" target="_blank"&gt;http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale/mx6qarm2?h=imx_v2015.04_4.1.15_1.0.0_ga&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Seems there is no way to use ddr test with DDR on CS1 without CS0,&lt;/P&gt;&lt;P&gt;but for performing test one can replace CS1 with CS0 and run tester on one board.&lt;/P&gt;&lt;P&gt;After finding correct calibration coefficients use them in other boards with DDR on CS1.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 03 Nov 2016 07:20:26 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2016-11-03T07:20:26Z</dc:date>
    <item>
      <title>DDR CS1 Boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR-CS1-Boot/m-p/623311#M94534</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In our design, we have given a solution based on i.MX6q with 2 GB DDR3 interfaced to MMDC's CS1, without CS0. &lt;/P&gt;&lt;P&gt;As per NXP support team, this method of mounting DDR on CS1 without CS0 is not recommended.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But we still explored options to booting using the above configuration and able to boot the Bootloader with below modifications to the DDR configuration and Bootloader code:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Enabled both CS0 and CS1 chip selects with address mirroring enabled.&lt;/LI&gt;&lt;LI&gt;CS0 address space is set from 0x10000000 to 0x50000000 (1GB).&lt;/LI&gt;&lt;LI&gt;CS1 address space is set from 0x50000000 to 0x90000000 (1GB).&lt;/LI&gt;&lt;LI&gt;Bootloader is built to execute from CS1 address space.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are not able to extend the CS0 and CS1 address space to 2GB boundary (CS0:0x10000000 to 0x90000000. CS1:0x90000000 to end of memory). With this configuration Bootloader doesn't boot from CS1.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can someone give more information on what is actually happening when we set the MMDC controller with above configuration?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And also we are not able to boot Linux, although we changed the address in Makefile.boot. Are there any other Linux BSP changes to be done?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks and Regards,&lt;/P&gt;&lt;P&gt;Vishakh&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 03 Nov 2016 05:22:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR-CS1-Boot/m-p/623311#M94534</guid>
      <dc:creator>vishakh</dc:creator>
      <dc:date>2016-11-03T05:22:40Z</dc:date>
    </item>
    <item>
      <title>Re: DDR CS1 Boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR-CS1-Boot/m-p/623312#M94535</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Vishakh&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for configuration of CS0 and CS1 address space with 2GB one can refer to&lt;/P&gt;&lt;P&gt;arm2 board (sch-27016)&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/329819"&gt;i.MX6Q/DL 4GB DDR3 RAM porting&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/431885"&gt;IMX6 surpport 4GB DDR3 reference BRD and length excel&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;L4.1.15 arm2 dts file: imx6q-arm2.dts&lt;BR /&gt;git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts/imx6q-arm2.dts?h=imx_4.1.15_1.0.0_ga&lt;BR /&gt;uboot imx_v2015.04 *.cgf file&lt;BR /&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fgit.freescale.com%2Fgit%2Fcgit.cgi%2Fimx%2Fuboot-imx.git%2Ftree%2Fboard%2Ffreescale%2Fmx6qarm2%3Fh%3Dimx_v2015.04_4.1.15_1.0.0_ga" rel="nofollow" target="_blank"&gt;http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale/mx6qarm2?h=imx_v2015.04_4.1.15_1.0.0_ga&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Seems there is no way to use ddr test with DDR on CS1 without CS0,&lt;/P&gt;&lt;P&gt;but for performing test one can replace CS1 with CS0 and run tester on one board.&lt;/P&gt;&lt;P&gt;After finding correct calibration coefficients use them in other boards with DDR on CS1.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 03 Nov 2016 07:20:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR-CS1-Boot/m-p/623312#M94535</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2016-11-03T07:20:26Z</dc:date>
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