topic LPDDR2 - DRAM_RESET in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/LPDDR2-DRAM-RESET/m-p/622224#M94357 <HTML><HEAD></HEAD><BODY><P>1.What is the meaning of DRAM_RESET signal when using IMX6Q &nbsp;with LPDDR2?</P><P>2. Can I leave it floating or do i need a pull down resistor?</P><P>Regards, Eli</P></BODY></HTML> Sun, 18 Dec 2016 10:29:03 GMT eliaz 2016-12-18T10:29:03Z LPDDR2 - DRAM_RESET https://community.nxp.com/t5/i-MX-Processors/LPDDR2-DRAM-RESET/m-p/622224#M94357 <HTML><HEAD></HEAD><BODY><P>1.What is the meaning of DRAM_RESET signal when using IMX6Q &nbsp;with LPDDR2?</P><P>2. Can I leave it floating or do i need a pull down resistor?</P><P>Regards, Eli</P></BODY></HTML> Sun, 18 Dec 2016 10:29:03 GMT https://community.nxp.com/t5/i-MX-Processors/LPDDR2-DRAM-RESET/m-p/622224#M94357 eliaz 2016-12-18T10:29:03Z Re: LPDDR2 - DRAM_RESET https://community.nxp.com/t5/i-MX-Processors/LPDDR2-DRAM-RESET/m-p/622225#M94358 <HTML><HEAD></HEAD><BODY><P>Hi Eli</P><P></P><P>according to Table 2-1. DDR recommendations i.MX6 System Development User’s</P><P>Guide it should be left unconnected.</P><P><A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fcache.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fuser_guide%2FIMX6DQ6SDLHDG.pdf" rel="nofollow" target="_blank">http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf</A></P><P></P><P>Best regards<BR />igor<BR />-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Sun, 18 Dec 2016 23:26:04 GMT https://community.nxp.com/t5/i-MX-Processors/LPDDR2-DRAM-RESET/m-p/622225#M94358 igorpadykov 2016-12-18T23:26:04Z