<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic uboot-imx atheros PHY driver config question? in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/uboot-imx-atheros-PHY-driver-config-question/m-p/622093#M94324</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;We encountered the voltage peak issue while doing the IEEE PHY conformance test, which has to do with the AR8033 register (SetDes Test and System Mode Control) setting in u-boot.&amp;nbsp;&lt;/SPAN&gt;After looking into the commit info (from git://git.freescale.com/imx/uboot-imx.git, branch l5.1.1_2.1.0-ga ), we found the PHY configuration has to do with the following commits, which are from NXP developers.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;Is there's anyone from NXP who can help explain why the register SerDES test and System Mode control is set to&amp;nbsp;&lt;SPAN&gt;0x3D47 learned from Andy Fleming commit info? When we checked the AR8033 spec (see the attachment), it is said the reserved bits would be set to 0 after a HW or SW reset.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thank you&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;commit 9082eeac5de1335d663016668c9b89c290f5c79b&lt;BR /&gt;&lt;SPAN&gt;Author: Andy Fleming &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:afleming@freescale.com" target="_blank"&gt;afleming@freescale.com&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;Date: Thu Apr 7 21:56:05 2011 -0500&lt;/P&gt;
&lt;P&gt;phylib: Add a bunch of PHY drivers from tsec&lt;/P&gt;
&lt;P&gt;The tsec driver had a bunch of PHY drivers already written. This&lt;BR /&gt;converts them all into PHY Lib drivers, and serves as the first&lt;BR /&gt;set of PHY drivers for PHY Lib.&lt;/P&gt;
&lt;P&gt;While doing that, cleaned up a number of magic numbers (though&lt;BR /&gt;not all of them, as PHY vendors like to keep their numbers as&lt;BR /&gt;magical as possible). Also, noticed that almost all of the&lt;BR /&gt;vitesse/cicada PHYs had the same config/parse/startup functions,&lt;BR /&gt;so those have been collapsed into one.&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Signed-off-by: Andy Fleming &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:afleming@freescale.com" target="_blank"&gt;afleming@freescale.com&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; Signed-off-by: Kumar Gala &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:galak@kernel.crashing.org" target="_blank"&gt;galak@kernel.crashing.org&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; Acked-by: Detlev Zundel &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:dzu@denx.de" target="_blank"&gt;dzu@denx.de&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;+/*&lt;BR /&gt;+ * Atheros PHY drivers&lt;BR /&gt;+ *&lt;BR /&gt;+ * This program is free software; you can redistribute it and/or&lt;BR /&gt;+ * modify it under the terms of the GNU General Public License as&lt;BR /&gt;+ * published by the Free Software Foundation; either version 2 of&lt;BR /&gt;+ * the License, or (at your option) any later version.&lt;BR /&gt;+ *&lt;BR /&gt;+ * This program is distributed in the hope that it will be useful,&lt;BR /&gt;+ * but WITHOUT ANY WARRANTY; without even the implied warranty of&lt;BR /&gt;+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the&lt;BR /&gt;+ * GNU General Public License for more details.&lt;BR /&gt;+ *&lt;BR /&gt;+ * You should have received a copy of the GNU General Public License&lt;BR /&gt;+ * along with this program; if not, write to the Free Software&lt;BR /&gt;+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,&lt;BR /&gt;+ * MA 02111-1307 USA&lt;BR /&gt;+ *&lt;BR /&gt;+ * Copyright 2011 Freescale Semiconductor, Inc.&lt;BR /&gt;+ * author Andy Fleming&lt;BR /&gt;+ *&lt;BR /&gt;+ */&lt;BR /&gt;+#include &amp;lt;phy.h&amp;gt;&lt;BR /&gt;+&lt;BR /&gt;+static int ar8021_config(struct phy_device *phydev)&lt;BR /&gt;+{&lt;BR /&gt;+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);&lt;BR /&gt;+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);&lt;BR /&gt;+&lt;BR /&gt;+ return 0;&lt;BR /&gt;+}&lt;BR /&gt;+&lt;BR /&gt;+struct phy_driver AR8021_driver = {&lt;BR /&gt;+ .name = "AR8021",&lt;BR /&gt;+ .uid = 0x4dd040,&lt;BR /&gt;+ .mask = 0xfffff0,&lt;BR /&gt;+ .features = PHY_GBIT_FEATURES,&lt;BR /&gt;+ .config = ar8021_config,&lt;BR /&gt;+ .startup = genphy_startup,&lt;BR /&gt;+ .shutdown = genphy_shutdown,&lt;BR /&gt;+};&lt;BR /&gt;+&lt;BR /&gt;+int phy_atheros_init(void)&lt;BR /&gt;+{&lt;BR /&gt;+ phy_register(&amp;amp;AR8021_driver);&lt;BR /&gt;+&lt;BR /&gt;+ return 0;&lt;BR /&gt;+}&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;commit 626ee1e32eeb4fc89e0f406d6067ed6e71d8302f&lt;BR /&gt;&lt;SPAN&gt;Author: Shengzhou Liu &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:Shengzhou.Liu@freescale.com" target="_blank"&gt;Shengzhou.Liu@freescale.com&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;Date: Thu Aug 8 16:33:35 2013 +0800&lt;/P&gt;
&lt;P&gt;phylib: update atheros ar803x phy&lt;/P&gt;
&lt;P&gt;As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the&lt;BR /&gt;common driver. Currently AR8031_driver didn't work for AR8033,&lt;BR /&gt;hence updated it to have it work on AR8031/AR8033.&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Signed-off-by: Shengzhou Liu &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:Shengzhou.Liu@freescale.com" target="_blank"&gt;Shengzhou.Liu@freescale.com&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c&lt;BR /&gt;index 0f2dfd6..7a1453f 100644&lt;BR /&gt;--- a/drivers/net/phy/atheros.c&lt;BR /&gt;+++ b/drivers/net/phy/atheros.c&lt;BR /&gt;@@ -48,11 +48,11 @@ static struct phy_driver AR8021_driver = {&lt;BR /&gt;};&lt;/P&gt;
&lt;P&gt;static struct phy_driver AR8031_driver = {&lt;BR /&gt;- .name = "AR8031",&lt;BR /&gt;+ .name = "AR8031/AR8033",&lt;BR /&gt;.uid = 0x4dd074,&lt;BR /&gt;.mask = 0xfffff0,&lt;BR /&gt;.features = PHY_GBIT_FEATURES,&lt;BR /&gt;- .config = genphy_config,&lt;BR /&gt;+ .config = ar8021_config,&lt;BR /&gt;.startup = genphy_startup,&lt;BR /&gt;.shutdown = genphy_shutdown,&lt;BR /&gt;};&lt;/P&gt;</description>
    <pubDate>Wed, 19 May 2021 17:57:50 GMT</pubDate>
    <dc:creator>kenlin</dc:creator>
    <dc:date>2021-05-19T17:57:50Z</dc:date>
    <item>
      <title>uboot-imx atheros PHY driver config question?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/uboot-imx-atheros-PHY-driver-config-question/m-p/622093#M94324</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;We encountered the voltage peak issue while doing the IEEE PHY conformance test, which has to do with the AR8033 register (SetDes Test and System Mode Control) setting in u-boot.&amp;nbsp;&lt;/SPAN&gt;After looking into the commit info (from git://git.freescale.com/imx/uboot-imx.git, branch l5.1.1_2.1.0-ga ), we found the PHY configuration has to do with the following commits, which are from NXP developers.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;Is there's anyone from NXP who can help explain why the register SerDES test and System Mode control is set to&amp;nbsp;&lt;SPAN&gt;0x3D47 learned from Andy Fleming commit info? When we checked the AR8033 spec (see the attachment), it is said the reserved bits would be set to 0 after a HW or SW reset.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thank you&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;commit 9082eeac5de1335d663016668c9b89c290f5c79b&lt;BR /&gt;&lt;SPAN&gt;Author: Andy Fleming &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:afleming@freescale.com" target="_blank"&gt;afleming@freescale.com&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;Date: Thu Apr 7 21:56:05 2011 -0500&lt;/P&gt;
&lt;P&gt;phylib: Add a bunch of PHY drivers from tsec&lt;/P&gt;
&lt;P&gt;The tsec driver had a bunch of PHY drivers already written. This&lt;BR /&gt;converts them all into PHY Lib drivers, and serves as the first&lt;BR /&gt;set of PHY drivers for PHY Lib.&lt;/P&gt;
&lt;P&gt;While doing that, cleaned up a number of magic numbers (though&lt;BR /&gt;not all of them, as PHY vendors like to keep their numbers as&lt;BR /&gt;magical as possible). Also, noticed that almost all of the&lt;BR /&gt;vitesse/cicada PHYs had the same config/parse/startup functions,&lt;BR /&gt;so those have been collapsed into one.&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Signed-off-by: Andy Fleming &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:afleming@freescale.com" target="_blank"&gt;afleming@freescale.com&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; Signed-off-by: Kumar Gala &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:galak@kernel.crashing.org" target="_blank"&gt;galak@kernel.crashing.org&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; Acked-by: Detlev Zundel &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:dzu@denx.de" target="_blank"&gt;dzu@denx.de&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;+/*&lt;BR /&gt;+ * Atheros PHY drivers&lt;BR /&gt;+ *&lt;BR /&gt;+ * This program is free software; you can redistribute it and/or&lt;BR /&gt;+ * modify it under the terms of the GNU General Public License as&lt;BR /&gt;+ * published by the Free Software Foundation; either version 2 of&lt;BR /&gt;+ * the License, or (at your option) any later version.&lt;BR /&gt;+ *&lt;BR /&gt;+ * This program is distributed in the hope that it will be useful,&lt;BR /&gt;+ * but WITHOUT ANY WARRANTY; without even the implied warranty of&lt;BR /&gt;+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the&lt;BR /&gt;+ * GNU General Public License for more details.&lt;BR /&gt;+ *&lt;BR /&gt;+ * You should have received a copy of the GNU General Public License&lt;BR /&gt;+ * along with this program; if not, write to the Free Software&lt;BR /&gt;+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,&lt;BR /&gt;+ * MA 02111-1307 USA&lt;BR /&gt;+ *&lt;BR /&gt;+ * Copyright 2011 Freescale Semiconductor, Inc.&lt;BR /&gt;+ * author Andy Fleming&lt;BR /&gt;+ *&lt;BR /&gt;+ */&lt;BR /&gt;+#include &amp;lt;phy.h&amp;gt;&lt;BR /&gt;+&lt;BR /&gt;+static int ar8021_config(struct phy_device *phydev)&lt;BR /&gt;+{&lt;BR /&gt;+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);&lt;BR /&gt;+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);&lt;BR /&gt;+&lt;BR /&gt;+ return 0;&lt;BR /&gt;+}&lt;BR /&gt;+&lt;BR /&gt;+struct phy_driver AR8021_driver = {&lt;BR /&gt;+ .name = "AR8021",&lt;BR /&gt;+ .uid = 0x4dd040,&lt;BR /&gt;+ .mask = 0xfffff0,&lt;BR /&gt;+ .features = PHY_GBIT_FEATURES,&lt;BR /&gt;+ .config = ar8021_config,&lt;BR /&gt;+ .startup = genphy_startup,&lt;BR /&gt;+ .shutdown = genphy_shutdown,&lt;BR /&gt;+};&lt;BR /&gt;+&lt;BR /&gt;+int phy_atheros_init(void)&lt;BR /&gt;+{&lt;BR /&gt;+ phy_register(&amp;amp;AR8021_driver);&lt;BR /&gt;+&lt;BR /&gt;+ return 0;&lt;BR /&gt;+}&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;commit 626ee1e32eeb4fc89e0f406d6067ed6e71d8302f&lt;BR /&gt;&lt;SPAN&gt;Author: Shengzhou Liu &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:Shengzhou.Liu@freescale.com" target="_blank"&gt;Shengzhou.Liu@freescale.com&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;Date: Thu Aug 8 16:33:35 2013 +0800&lt;/P&gt;
&lt;P&gt;phylib: update atheros ar803x phy&lt;/P&gt;
&lt;P&gt;As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the&lt;BR /&gt;common driver. Currently AR8031_driver didn't work for AR8033,&lt;BR /&gt;hence updated it to have it work on AR8031/AR8033.&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Signed-off-by: Shengzhou Liu &amp;lt;&lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:Shengzhou.Liu@freescale.com" target="_blank"&gt;Shengzhou.Liu@freescale.com&lt;/A&gt;&lt;SPAN&gt;&amp;gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c&lt;BR /&gt;index 0f2dfd6..7a1453f 100644&lt;BR /&gt;--- a/drivers/net/phy/atheros.c&lt;BR /&gt;+++ b/drivers/net/phy/atheros.c&lt;BR /&gt;@@ -48,11 +48,11 @@ static struct phy_driver AR8021_driver = {&lt;BR /&gt;};&lt;/P&gt;
&lt;P&gt;static struct phy_driver AR8031_driver = {&lt;BR /&gt;- .name = "AR8031",&lt;BR /&gt;+ .name = "AR8031/AR8033",&lt;BR /&gt;.uid = 0x4dd074,&lt;BR /&gt;.mask = 0xfffff0,&lt;BR /&gt;.features = PHY_GBIT_FEATURES,&lt;BR /&gt;- .config = genphy_config,&lt;BR /&gt;+ .config = ar8021_config,&lt;BR /&gt;.startup = genphy_startup,&lt;BR /&gt;.shutdown = genphy_shutdown,&lt;BR /&gt;};&lt;/P&gt;</description>
      <pubDate>Wed, 19 May 2021 17:57:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/uboot-imx-atheros-PHY-driver-config-question/m-p/622093#M94324</guid>
      <dc:creator>kenlin</dc:creator>
      <dc:date>2021-05-19T17:57:50Z</dc:date>
    </item>
  </channel>
</rss>

